New constraints requirement in 20.2 pro

[RZhen11]

Dear all,

I have a project with a lot of weirdness in 18.1 std edition. I went to 20.2 pro for exploration. All IP cores are regenerated.

First thing I found is "timing not met", timing analyzer reports whole lot of violations in clock crossing with one end at XCVRs.

The project was timing closed in std edition. And I imagine the .sdc in XCVR (auto generated) is sufficient).

Is this expected?

Some examples of the required new constraints:

set_false_path -from [get_clocks {Rx_Serdes|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|out_clkdiv_rx}] -to [get_clocks {SPI_Clk_v}]
set_false_path -from [get_clocks {Serdes_inst|TX_loop[0].SerdesTX_inst|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_tx_cgb.inst_twentynm_hssi_pma_tx_cgb}] -to [get_clocks {Serdes_inst|TxClk_inst|iopll_0|altera_iopll_i|twentynm_pll|outclk[0]}]

Please advise, 

[KhaiChein_Y_Intel]

Hi,

Can you share the design for investigation?

Thanks.

Best regards,

KhaiY

[RZhen11]

Hi KhaiChein,

Thanks for your attention, unfortunately I can't put the entire project on public domain.

So far, I don't see much benefits for using PRO edition for my project.

I'll probably roll back and stick with STD edition.

Regards,

Ethan

[KhaiChein_Y_Intel]

Hi Ethan,

Sure. I will transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.

Best regards,

KhaiY