Hi,before trying to stop me from it. I know very well why I want ring oscillators and have used them in a competitor's FPGA already, where it was easier to introduce them. Now I wanted to try Altera, specifically the Stratix IV GX on a Terasic DE4 board, but seem to not get it working. I use vhdl generate statements to make more than 1000 of them, so either they get reduced to 1 and I can't find that in the Technology Map Viewer (is there some way to preserve some names and hierarchy?), or they get completely removed. However, most of the time I see the wanted design in RTL Viewer. So I disabled all kind of synthesis settings that could lead to merging, but that didn't change anything. None of these examples worked for me: - After fixing the syntactical problems in http://www.alterawiki.com/wiki/ring_oscillator they looked ok in RTL Viewer but seemed to be gone after. I did only try instances of the verilog source. Is there more to it, required from the constraints etc.? It didn't look like that for me, and I am especially not trusting that design much if it doesn't even synthesize to begin with. - Trying from the snippet there, and adding syn_keep and/or keep didn't help: http://www.alteraforum.com/forum/showthread.php?t=42155 - Multiple things I found, like using LUT_INPUT and LUT_OUTPUT and experimented with all the attributes/constraints. I checked numerous posts and there seem to be options of using LCELL combinations, or LUT_INPUT/LUT_OUTPUT, or it might even be possible to use wysiwyg.stratixiv_components.all. Which of them is the most straightforward solution, and might some of them not even work for me (Stratix IV)? Overall I'd prefer any LUT2 to 4 that are connected to itself as a RO, with one LUT-state being used to disable/enable the oscillation. My last try of that is shown below the text. I did not yet try instantiating components from wysiwyg.stratixiv_components.all as I first need to find and read documentation how to do that to get what I want. Would that be the solution or am I wasting just more time with that? Thanks for any help / hints.
LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; library altera; use altera.altera_syn_attributes.all; ENTITY LUT_for_RO IS PORT ( a : IN STD_LOGIC; b : IN STD_LOGIC; c : IN STD_LOGIC; d : IN STD_LOGIC; o : OUT STD_LOGIC); END LUT_for_RO; ARCHITECTURE arch OF LUT_for_RO IS SIGNAL as, bs, cs, ds, os: STD_LOGIC; COMPONENT LUT_INPUT PORT (a_in : IN STD_LOGIC; a_out: OUT STD_LOGIC); END COMPONENT; COMPONENT LUT_OUTPUT PORT (a_in : IN STD_LOGIC; a_out : OUT STD_LOGIC); END COMPONENT; attribute keep : boolean; attribute preserve : boolean; --attribute syn_keep : string; attribute keep of as : signal is true; attribute keep of bs : signal is true; attribute keep of cs : signal is true; attribute keep of ds : signal is true; attribute keep of os : signal is true; attribute preserve of as : signal is true; attribute preserve of bs : signal is true; attribute preserve of cs : signal is true; attribute preserve of ds : signal is true; attribute preserve of os : signal is true; BEGIN LUT_a : LUT_INPUT PORT MAP ( a_in => a, a_out => as); LUT_b : LUT_INPUT PORT MAP ( a_in => b, a_out => bs); LUT_c : LUT_INPUT PORT MAP ( a_in => c, a_out => cs); LUT_d : LUT_INPUT PORT MAP ( a_in => d, a_out => ds); os <= not as or not bs; LUT_o : LUT_OUTPUT PORT MAP ( a_in => os, a_out => o); END arch;
The shown code is only one overall instance of a single supposed-to-be ring oscillator. Yes I didn't use the c and d inputs. I just wanted to write it like a 4-input LUT, thus they are there. One level higher I instantiate multiple of these in a generate statement.
Why not use the example from ring oscillator? Just because it's Verilog? I'd just copy that and move on. : )I don't see anywhere in your code where it actually loops back? I synthesized it in Quartus and it shows the same thing. The Technology Map View shows three LUTs, as, bs and os, which looks correct. (Note that the keep attribute tries to keep that point as the output of a LUT or Register, i.e. so it can be tapped by SignalTap or something like that. It is not a stand-alone LUT. So in this case the OR gate gets absorbed into the LUT feeding point os.
The Verilog had some syntactical problems so I didn't trusted it very much and just tried it shortly (always_ff instead of always and i++ instead of i = i+1), after fixing them it didn't work...And oops, sorry the code I posted was at some non functional intermediate state, believe me I also had it with feedback. I will correct the first post to the one I tried last. //edit: OK, sorry, the code was actually correct after all, I externally then instantiated it this way:
activity_ROs : for i in 0 to amount-1 generate begin ro_inv: LUT_for_RO port map (a => self_s(i), b => enable_i, c => '0', d => '0', o => self_s(i)); end generate;Maybe the problem is the other parts of the design, so I overlooked it in Technology Viewer. But that would mean that at least all multiple instances get removed. How can I keep all my 1000s of ROs? //edit2: Okay I have to apologize, I saw it was System Verilog after all. Let's see if this helps, hope I can also instantiate it in a VHDL design
OK I tried it with the original system verilog source and instantiate 1200 of them.Some Ports from the DE4 Board (Buttons and Switches) have these ROs in their Fanout. The Technology Map Viewer shows absolutely nothing connected to these Ports. So everything that was there got removed, including the ROs of course. So at least I could narrow down the problem, and it doesn't seem to be a logic merging problem.