Not able to do fitting design with Quartus 22.1

[VSavi3]

Hi,

I am able to fit the attached design with Version 22.1std.0 Build 915 10/25/2022 SC Standard Edition.

However, I can fit the design with ease in Version 19.1.0 Build 670 09/22/2019 SJ Standard Edition

Please suggest what changes required to in settings file.

Attached qsf file (extension changed to .txt to attach here) and report files both versions.

The error I got with Version 22.1std.0 Build 915 10/25/2022 SC Standard Edition is

"Error (170011): Design contains 249203 blocks of type combinational node. However, the device contains only 227120 blocks."

Please note, due to confidentiality, I can't make available the source codes for these builds.

Regards,

Vikram

[ShengN_Intel]

Hi Vikram,

By comparing between the 19.1 and 22.1 .qsf, there're much differences in partition assignment may be have to recheck on this.

The error message suggests that have to reduce the combinational node in order to fit.

Thanks,

Best Regards,

Sheng

[ShengN_Intel]

Hi,

Any further update or concern?

Thanks,

Best Regards,

Sheng

[Vikram_Savitrimane]

The problem still exist in 22.1 and in all later versions of Quartus after 19.1.

So for us the last working Quartus software is 19.1.

I appreciate, if Intel Quartus team have a deep look in to it and get back to us with latest working version.

Regards,

Vikram

[ShengN_Intel]

Hi,

I had compared between the v19.1 and v22.1 .qsf and noticed there're differences between the v19.1 and v22.1 .qsf. in terms of partition and logic lock region. Is that the design used in v19.1 and v22.1 are exactly the same? Is that the partition and logic lock region are exactly the same as well? If no, then that's normal to get different compilation result for both v19.1 and v22.1.

Thanks,

Best Regards,

Sheng

[ShengN_Intel]

Hi,

Any further update or concern?

Thanks,

Best Regards,

Sheng

[VSavi3]

Yes, the status is same. 22.1 we're not able to use.

Regards,

Vikram

[ShengN_Intel]

Hi,

So you mean the design used for both 19.1 and 22.1 are exactly the same? But why the .qsf provided for both 19.1 and 22.1 showing differently at the partition and logic lock assignment? In GUI, can you go to Assignments -> Design Partitions Window and Logic Lock Regions Window to confirm about it.

Need to make sure the design used for both 19.1 and 22.1 are exactly the same.

Thanks,

Best Regards,

Sheng

[VSavi3]

Hi, yes design is exactly the same. Partition is not the issue, with/or without partition assignment just trying to fit in 19.1 goes well without any issue. With later than 19.1 Quartus (including latest 21.1), we seeing the error we mentioned.

So we like to know, to fit in later version of Quartus than 19.1 what changes in qsf we need to do.

Regards,

Vikram

[ShengN_Intel]

Hi Vikram,

Forgot to mention I also noticed that there're different at this setting Auto Packed Registers. Version 19.1 use 'Normal' while version 22.1 use 'Minimize Area'. Make sure fitter advanced settings are the same as well.

Thanks,

Best Regards,

Sheng

[VSavi3]

Hi,

Will check this and come back to by end of next week.

Regards,

Vikram

[ShengN_Intel]

Hi Vikram,

Any further update on the previous post community.intel.com/t5/Intel-Quartus-Prime-Software/Not-able-to-do-fitting-design-with-Quartus-22-1/m-p/1505446#M79353

[VSavi3]

Hi,

I have indeed used Normal settings for Auto Packed Registers. Attached is the freshly generated reports with 22.1.

The problem is still the same. 

Please check if anything in the settings need to modified.

Regards,

Vikram

[ShengN_Intel]

Hi,

Then I think probably have to get a larger device. Migration from 19.1 to 22.1 most likely will involve many things being upgraded which probably will cause higher utilization. So now I got both fit reports of 19.1 and 22.1. By comparing between Fitter Resource Usage Summary of 19.1 and 22.1, clearly can see that it's quite full for 22.1 compared to 19.1 even ALMs utilization (114%) also had been exceeded 100% (image below). I would suggest that getting a bigger device.

Thanks,

Sheng

[VSavi3]

Hi,

I reckon, this is not the solution I am looking for. If its easily fits in earlier version of software, then all that we can conclude is the latest version of software have bug.

So unless Intel comes back with proper fix of the bug we can't use the latest software.

Regards,

Vikram

[ShengN_Intel]

How about try with the settings below and see:

Optimization Mode:

Area

Advanced Fitter Settings:

ALM Register Packing Effort - High

Fit Attempts to Skip - 2

Perform Logic to Memory Mapping for Fitting - on

Perform Physical Synthesis for Combinational Logic for Fitting - on

Placement Effort Multiplier - 4.0

Auto Packed Registers - Minimize Area with Chains

One more is can you try to do another migration totally without any ip upgradation by ignoring the IP Upgrade Recommended box. Any difference?

Thanks,

Best Regards,

Sheng

[VSavi3]

Hi,

Please find the results of the run with your following suggestions.

---

Optimization Mode:

Area

Advanced Fitter Settings:

ALM Register Packing Effort - High

Fit Attempts to Skip - 2

Perform Logic to Memory Mapping for Fitting - on

Perform Physical Synthesis for Combinational Logic for Fitting - on

Placement Effort Multiplier - 4.0

Auto Packed Registers - Minimize Area with Chains

---

Regards,

Vikram

[ShengN_Intel]

Or try go to Project -> Clean Project and see

Thanks,

Sheng

[VSavi3]

Hi,

Clean build too gave the same error.

Regards,

Vikram

[ShengN_Intel]

Hi,

Could you provide the 19.1 design for bug identifying? Design is needed for engineering team to identify the bug as well.

You can provide the design privately to my email qi.sheng.ng@intel.com and will be treated confidentially.

Thanks,

Best Regards,

Sheng

[VSavi3]

Hi,

We can't provide the design IP.

Regards,

Vikram