Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
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Onchip FIFO Memory Core [Avalon-MM Write Slave to Avalon-MM Read Slave]: Help In NIOS Programming Code

SS5
Novice
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Hello,

I want to write 32-bit data into FIFO and read the data from FIFO.

So, I have followed this FIFO configuration :Aalon-MM write slave to Avalon-MM read slave.

 

Questions to be clarified:

  1. I have enabled "backpressure" how to set in wait request signal in NIOS (0`s (deserted) or 1`s (asserted)).

2. i want example code to read the data from FIFO. I have tried but its throwing error. "FIFO_0_IN_BASE" is undeclared.

in which file i can find Base address and control address for read operation.

Please anyone guide me.

 

#include "sys/alt_stdio.h" #include "alt_types.h" #include<io.h> #include<system.h> #include<stdio.h> #include "altera_avalon_pio_regs.h" #include "altera_avalon_fifo.h" #include "altera_avalon_fifo_util.h" #include "altera_avalon_fifo_regs.h"   #define FIFO_0_IN_BASE 0x3000 #define ctrl_address 0x3040     int main() {   int result,i=0; int *data=0;   IOWR(ENABLE_BASE, 0, 0x1); // Enable the counter alt_printf("Hello from Nios II!\n"); // Send Hello World to the JTAG UART   while(1) { *data = IORD_ALTERA_AVALON_FIFO_DATA(FIFO_0_IN_BASE); printf("%d\n",*data); } return 0; }

 

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a_x_h_75
New Contributor III
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The base addresses are defined in the 'system.h' file (that you already have in your #include list).

 

Cheers,

Alex

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SS5
Novice
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Hello,

Again, i am facing the same problem. Data is not in proper sequence in NIOS, i am unable to debug. I am attaching my Block diagram and NIOS code. Please anyone guide.

For Qsys design, please refer above question.

 

Nios Console too attached

Nios.JPG

 

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