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Honored Contributor I

One or two bank memories issue

I am testing "hello_wolrd" example for cyclone V by using OpenCL sdk and "c5soc" profile board on the compiler. I followed the getting started guide and it works perfectly.  


However, when I try to use another board profile as "c5soc_sharedonly" this does not work, the issue is exposed at the moment of running the host application and this indicate a "different name of device issue", so based on this issue, I edit the "board_spec.xml" name field to change just for c5soc (deleting "_sharedonly" part), and also the folder of the board was edited with c5soc only. By avoiding to have conflict with c5soc original board profile, I move the folder to another place. And again I compile but this time using "c5soc" board profile ( c5soc_sharedonly edited) its compile correctly but this time when I try to run host application linux get freezed.  


root@socfpga:~# ./host -sh: ./host: cannot execute binary file root@socfpga:~# chmod +x host root@socfpga:~# source ./ Error: could not insert module /home/root/opencl_arm32_rte/board/c5soc/driver/aclsoc_drv.ko: File exists root@socfpga:~# ./host Querying platform for info: ========================== CL_PLATFORM_NAME = Altera SDK for OpenCL CL_PLATFORM_VENDOR = Altera Corporation CL_PLATFORM_VERSION = OpenCL 1.0 Altera SDK for OpenCL, Version 16.0 Querying device for info: ======================== CL_DEVICE_NAME = c5socCyclone V SoC Development Kit CL_DEVICE_VENDOR = Altera Corporation CL_DEVICE_VENDOR_ID = 4466 CL_DEVICE_VERSION = OpenCL 1.0 Altera SDK for OpenCL, Version 16.0 CL_DRIVER_VERSION = 16.0 CL_DEVICE_ADDRESS_BITS = 64 CL_DEVICE_AVAILABLE = true CL_DEVICE_ENDIAN_LITTLE = true CL_DEVICE_GLOBAL_MEM_CACHE_SIZE = 32768 CL_DEVICE_GLOBAL_MEM_CACHELINE_SIZE = 0 CL_DEVICE_GLOBAL_MEM_SIZE = 1073741824 CL_DEVICE_IMAGE_SUPPORT = true CL_DEVICE_LOCAL_MEM_SIZE = 16384 CL_DEVICE_MAX_CLOCK_FREQUENCY = 1000 CL_DEVICE_MAX_COMPUTE_UNITS = 1 CL_DEVICE_MAX_CONSTANT_ARGS = 8 CL_DEVICE_MAX_CONSTANT_BUFFER_SIZE = 268435456 CL_DEVICE_MAX_WORK_ITEM_DIMENSIONS = 3 CL_DEVICE_MEM_BASE_ADDR_ALIGN = 8192 CL_DEVICE_MIN_DATA_TYPE_ALIGN_SIZE = 1024 CL_DEVICE_PREFERRED_VECTOR_WIDTH_CHAR = 4 CL_DEVICE_PREFERRED_VECTOR_WIDTH_SHORT = 2 CL_DEVICE_PREFERRED_VECTOR_WIDTH_INT = 1 CL_DEVICE_PREFERRED_VECTOR_WIDTH_LONG = 1 CL_DEVICE_PREFERRED_VECTOR_WIDTH_FLOAT = 1 CL_DEVICE_PREFERRED_VECTOR_WIDTH_DOUBLE = 0 Command queue out of order? = false Command queue profiling enabled? = true Using AOCX: hello_world.aocx Reprogramming device with handle 1  


I am thinking that the RTE running over SOC-FPGA linux os is just compatible with two banks of ram memory project, because the c5soc_sharedonly profile has one bank memory and it is the only difference with c5soc board profile. 


Someone has more information related to this. I will be deeply thankful for any help.
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Honored Contributor I

I got the solution.  


As I am using other c5soc profile board, it is needed to reprogram with aocl 

1) Run comand: "aocl reprogram /dev/acl0 hello_world.aocx" 

2) Then you can run the c5soc shared only project: "./host" 


P.D: Always check the profile board that is running with coamand "aocl diagnose".