OpenCL Library Example 2 cannot be compiled

[RYang28]

Hi,

We recently purchased the Stratix 10 GX dev kit. We have successfully installed the required software for developing FPGA applications through OpenCL SDK.

Most examples under hld/example_aoc can be compiled and run successfully, but the library_example2 encountered errors.

I've attached the terminal output error message for your reference.

The reason behind this is that we want to develop a opencl kernel library to wrapper the Chip ID Intel Stratix 10 FPGA IP so that the chip id can be easily retrieved by a simple function call inside a kernel function.

Anyone can help? Thanks a lot!

[MuhammadAr_U_Intel]

Hi,

I am also seeing the same issue, I am suspecting this is due to example was created originally for older version of Quartus,

https://www.intel.com/content/www/us/en/programmable/support/support-resources/design-examples/design-software/opencl/library-design-example.html

I will further dig into it and update here.

Thanks,

Arslan

[MuhammadAr_U_Intel]

I checked the compilation for Arria10 GX works for compiler version 16.1 only.

With the latest version of compiler 18.1 one need to fix the RTL files as stated below.

Look for the "lsu_top' instance in files "sumOfElements.v" and "copyElement.v" and comment out following parameters. WIDTH, MWIDTH, INTENDED_DEVICE_FAMILY

//defparam lsu_local_bb0_ld_arrayidx3_promoted.WIDTH = 32;

//defparam lsu_local_bb0_ld_arrayidx3_promoted.MWIDTH = 512;

//defparam lsu_local_bb0_ld_arrayidx3_promoted.INTENDED_DEVICE_FAMILY = "Stratix V";

After this fix compilation is passed for target board Arria10 GX.

I will give a try to Stratix10 GX board now.

Thanks,

Arslan

[RYang28]

Hi Arslan,

Thanks a lot for your help!

In fact, I didn't find such parameters you mentioned here in both .v file. The examples I used are from the latest updates of Quartus Prime Pro (Version 18.1.1 Build 263 Pro Edition).

Looking forward to your result on the Stratix10 GX board.

I paste the parameters list of "lsu_top" in both files below.

sumOfElements.v

{

defparam lsu_local_bb0_ld_arrayidx3_promoted.AWIDTH = 28;

defparam lsu_local_bb0_ld_arrayidx3_promoted.WIDTH_BYTES = 4;

defparam lsu_local_bb0_ld_arrayidx3_promoted.MWIDTH_BYTES = 64;

defparam lsu_local_bb0_ld_arrayidx3_promoted.WRITEDATAWIDTH_BYTES = 64;

defparam lsu_local_bb0_ld_arrayidx3_promoted.ALIGNMENT_BYTES = 4;

defparam lsu_local_bb0_ld_arrayidx3_promoted.READ = 1;

defparam lsu_local_bb0_ld_arrayidx3_promoted.ATOMIC = 0;

defparam lsu_local_bb0_ld_arrayidx3_promoted.ATOMIC_WIDTH = 3;

defparam lsu_local_bb0_ld_arrayidx3_promoted.BURSTCOUNT_WIDTH = 6;

defparam lsu_local_bb0_ld_arrayidx3_promoted.KERNEL_SIDE_MEM_LATENCY = 2;

defparam lsu_local_bb0_ld_arrayidx3_promoted.MEMORY_SIDE_MEM_LATENCY = 131;

defparam lsu_local_bb0_ld_arrayidx3_promoted.USE_WRITE_ACK = 0;

defparam lsu_local_bb0_ld_arrayidx3_promoted.ENABLE_BANKED_MEMORY = 0;

defparam lsu_local_bb0_ld_arrayidx3_promoted.ABITS_PER_LMEM_BANK = 0;

defparam lsu_local_bb0_ld_arrayidx3_promoted.NUMBER_BANKS = 1;

defparam lsu_local_bb0_ld_arrayidx3_promoted.LMEM_ADDR_PERMUTATION_STYLE = 0;

defparam lsu_local_bb0_ld_arrayidx3_promoted.USEINPUTFIFO = 0;

defparam lsu_local_bb0_ld_arrayidx3_promoted.USECACHING = 0;

defparam lsu_local_bb0_ld_arrayidx3_promoted.USEOUTPUTFIFO = 1;

defparam lsu_local_bb0_ld_arrayidx3_promoted.FORCE_NOP_SUPPORT = 0;

defparam lsu_local_bb0_ld_arrayidx3_promoted.HIGH_FMAX = 1;

defparam lsu_local_bb0_ld_arrayidx3_promoted.ADDRSPACE = 1;

defparam lsu_local_bb0_ld_arrayidx3_promoted.STYLE = "STREAMING";

}

copyElement.v

{

defparam lsu_local_bb1_st_.AWIDTH = 32;

defparam lsu_local_bb1_st_.WIDTH_BYTES = 4;

defparam lsu_local_bb1_st_.MWIDTH_BYTES = 64;

defparam lsu_local_bb1_st_.WRITEDATAWIDTH_BYTES = 64;

defparam lsu_local_bb1_st_.ALIGNMENT_BYTES = 4;

defparam lsu_local_bb1_st_.READ = 0;

defparam lsu_local_bb1_st_.ATOMIC = 0;

defparam lsu_local_bb1_st_.ATOMIC_WIDTH = 3;

defparam lsu_local_bb1_st_.BURSTCOUNT_WIDTH = 5;

defparam lsu_local_bb1_st_.KERNEL_SIDE_MEM_LATENCY = 2;

defparam lsu_local_bb1_st_.MEMORY_SIDE_MEM_LATENCY = 16;

defparam lsu_local_bb1_st_.USE_WRITE_ACK = 1;

defparam lsu_local_bb1_st_.ENABLE_BANKED_MEMORY = 0;

defparam lsu_local_bb1_st_.ABITS_PER_LMEM_BANK = 0;

defparam lsu_local_bb1_st_.NUMBER_BANKS = 1;

defparam lsu_local_bb1_st_.LMEM_ADDR_PERMUTATION_STYLE = 0;

defparam lsu_local_bb1_st_.USEINPUTFIFO = 0;

defparam lsu_local_bb1_st_.USECACHING = 0;

defparam lsu_local_bb1_st_.USEOUTPUTFIFO = 1;

defparam lsu_local_bb1_st_.FORCE_NOP_SUPPORT = 0;

defparam lsu_local_bb1_st_.HIGH_FMAX = 1;

defparam lsu_local_bb1_st_.ADDRSPACE = 1;

defparam lsu_local_bb1_st_.STYLE = "BURST-COALESCED";

}

[MuhammadAr_U_Intel]

Hi,

I do see similar Errors as you when compiling the example2 targeting Stratix10 board.

At the moment I don't have any workaround suggestion for you on this example.

This is reported to Engineering team.

Thanks,

Arslan

[RYang28]

Hi Arslan,

Any feedback from the engineering team??

Thanks,

Robin

[bmorcos]

Hi RYang28,

Slightly tangential but...

I'm currently looking at adding an OpenCL library for Chip ID as well and I'm wondering if you had any success with this and could offer some advice.

Thanks,

Ben

[RYang28]

Hi Ben,

No success unfortunately...

Still waiting for Engineering team's reply.

[bmorcos]

I managed to get an OpenCL library working for the Unique Chip ID on a Cyclone V (DE1-SoC). I am hoping to make this public soon, once I get permission, and I will post a link when it's available!

[RYang28]

Hi bmorcos, That’s great! Looking forward to it. Thanks for sharing.

[bmorcos]

Not strictly a solution for you, but I've made an OpenCL wrapper for the Chip ID block for my Cyclone V (DE1-SoC). You will need to made some changes to get this running on Stratix but this should definitely be a good basis!

https://github.com/abr/c5soc-ocl-id

[RYang28]

Hi, Very appreciate your sharing of your work! It is a great help for us. I'll update you if we make any progress.