Hi,
I am adding read and write channels to OpenCL code and I see that they are correctly instantiated in <kernel>_system.v SV file, but there is no connection to the I/O. I am using a10_ref design as a baseline and have added the following to my board_spec.xml file:
<channels>
<interface name="data_port" port="data_out" type="streamsink" width="32" chan_id="data0_in"/>
<interface name="data_port" port="data_in" type="streamsource" width="32" chan_id="data0_out"/>
</channels>
In OpenCL code I declare these as IO channels:
# pragma OPENCL EXTENSION cl_intel_channels : enable
channel float DATA_IN __attribute__((depth(0)))
__attribute__((io("data0_in")));
channel float DATA_OUT __attribute__((depth(0)))
__attribute__((io("data0_out")));
float data_read = read_channel_intel(DATA_IN);
float data_to_send = test_value;
write_channel_intel(DATA_OUT,data_to_send);
One would expect these channels to be brought up to at least <kernel>_system.v SV file IO, but this is not so. The <kernel>_system instance has correct Avalon-ST sink and sources but they are "bolted up" to bit width translators and then trail ends.
If someone has done this, and I know some of you have, you know whom I am talking about: OpenCL certified board vendors; please share the knowledge.
Cheers.
