OpenCL for Arria 10 in Quartus 15.1

[Altera_Forum]

Hi, 

 I found there is an updated Quartus 15.1 available on Altera download site. Does it support OpenCL-FPGA mapping for new products like Arria 10? I'm asking since Arria 10 was mentioned in "Altera SDK for OpenCLGetting Started Guide":  • Quartus Prime Standard Edition software for devices other than Arria® 10 devices  • Quartus Prime Pro Edition software for Arria 10 devices  However, after downloading/installing the Quartus Prime Pro Edition, I don't see any Arria 10 related files in hld/board dir, s5_ref is the only supported device: $ ls /home/utils/altera/15.1_pro/hld/board c5soc custom_platform_toolkit dspba_sil_jtag dspba_sil_pcie s5_ref $aoc --list-boards Board list: s5_ref    If Arria 10 is supported in this build, what should I do to enable OpenCL compilation for Arria 10?  Thanks

[Altera_Forum]

Hi CnSha, 

 You will need to get the BSP for an Arria 10 board, add this into the hld/board directory and run "aocl install" to install this, the steps for this are all described in "Altera SDK for OpenCL Getting Started Guide".

[Altera_Forum]

Thanks Neil@SC 

 Another question: Is "BSP" something I should get from my FPGA Vendor separately? or it is the "Arria 10 device support" in the Quartus II installer?

[Altera_Forum]

The BSP is the Board Support Package supplied by the manufacturer of the board you are going to use. If you have designed your own board then you will have to create your own but Altera provides a called "Custom Platform Toolkit User Guide" document to help do this - https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/hb/opencl-sdk/ug_aocl_custom_platform_toolkit.pdf

[Altera_Forum]

Just to be clear and add some insight. Altera didn't get the A10 BSP for the A10 dev kit into the 15.1 so, this is something that needs to be requested from sales or through a service request. This BSP can be used as a guide towards building your own BSP for your own board or used on an A10 dev kit directly. 

 A10 requires Quartus Prime Pro because it uses QHD and PR in building the BSP with logic locked, timing closed partitions of the interface IP.

[Altera_Forum]

So what will happen if you copy arria_no_interface example BSP from AOCL15 to AOCL15.1? Will that still work? Does that mean it will not give correct area/speed estimate?

[Altera_Forum]

--- Quote Start ---  So what will happen if you copy arria_no_interface example BSP from AOCL15 to AOCL15.1? Will that still work? Does that mean it will not give correct area/speed estimate?  --- Quote End ---    Don't. THe 15.0 BSP doesn't used QHD or PR...it is a flat design that only supports JTAG programming on ES2 silicon with PCIe Gen2x8 and slower speed DDR. YOu want to start with the new BSP for 15.1 which has PCIe gen3x8, full speed DDR4 and QHD with PR support for programming.

[Altera_Forum]

Thank you for the reply. I am actually using Stratix V based boards, and was just trying to get an estimate on how much faster the Arria 10 could run compared to my Stratix V.  

 BTW: I am just wondering what do QHD and PR stand for?

[Altera_Forum]

SV is easier to port from 15.0 and 15.1. You will still need to update the IP to the newer version of Quartus, but that is typical in FPGA design. THis is also something that you only need Quartus Prime standard for. As for how much faster...depends on the code and how many floats you define. On average a 4x improvement from SV to A10 is common, but with alot of floats defined, I have seen an 8-10x improvement (specifically on things like genomics and CNN algos) 

 QHD = Quartus Heirarchal Design. A new feature in Quartus Pro Prime that allows building FPGAs hierarchally with timing closed, logic locked, and hardware preserved partitions that are IPXACT compatible PR = Partial reconfiguration. A method of reprogramming the FPGA dynamically...the most common case is over PCIe

[Altera_Forum]

Thank for the detailed answer Bill!