OpenCL guidelines to use physical pins of fpga

[Altera_Forum]

Cheers, 

 I am beginner with OpenCL SDK for cyclone V, I have experience building projects in Cyclone IV using NIOS soft core and fpga IP modules.  Now I am trying to use OpenCL in Cyclone V SOC-FPGA which has a hard processor inside. I finished successfully the first getting starter guide for OpenCL in cyclone V. I could run and edit the HelloWorld example.  However I have some questions: 1) The hello world example is compiled using aoc.exe and c5soc board profile installed by SDK OpenCL, when I perform a partial compilation (w/o build the hardware) I get a .aoco file and a folder called bin with quartus project. It is possible to edit the quartus project and then use this for make a complete compilation using .aoco file and quartus project edited? Currently, I edit the quartus project but I did this modifying the template in ALTERAOCLSDKROOT/board/c5soc-folder. I am thinking that it is not the best approach.   2) I would like to code in OpenCL using IO ports access (physical pins) of FPGA though OpenCL API functions available, but I was readying "Intel® FPGA SDK for OpenCL Custom Platform Toolkit User Guide" and this indicate me that I just able to use the interface defined in Board_spec.xml. So the question is: it is possible to add more interface as simple input output pins in fpga? If the answer is Yes, which reference guide I need to read to perform this?  I will be deeply thankful for any advising.

[Altera_Forum]

I'm not sure what you're trying to do in your first question, but as far as your second question is concerned, the answer is no. The BSP (the board_spec.xml file you mention) is responsible for configuring the I/O and creating "space" on the FPGA for the kernel hardware, which is created by compiling your kernel code with aoc. You can create OpenCL libraries that include RTL code, but there is no way to add or change the I/O of the device through OpenCL.

[Altera_Forum]

--- Quote Start ---  I'm not sure what you're trying to do in your first question, but as far as your second question is concerned, the answer is no. The BSP (the board_spec.xml file you mention) is responsible for configuring the I/O and creating "space" on the FPGA for the kernel hardware, which is created by compiling your kernel code with aoc. You can create OpenCL libraries that include RTL code, but there is no way to add or change the I/O of the device through OpenCL.  --- Quote End ---    Thank you very much for your answer. So the BSP (board_spec.xml) can be used to add more IO pins or interfaces, and then they will be available to use in openCL?  Concerning to first question. Ina general way I am asking for the correct work flow to develop a project by using OpenCL and IP or vhdl modules working together.   For instance, suppose that I want a project as the "hello world" example with the variation of modify the frequency of leds, to achieve this I compile the hello world example without do a complete compilation (not building hardware) and as result the aoc compilator generate me a .aoco file with the name of project and a folder with quartus project inside, now I can modify the frequency of leds by editing the verilog code from the quartus project generated, and then I save this and perform a complete compilation "building hardware" using .aoco file and quartus project modified in the folder. At the end I achieve the building of the project but I am not sure if this is the correct way because I can achieve the same task by editing in the altera board package folder the quartus project template and edit in the same way. I am pretty confuse with the correct work flow to develop a opencl project with cyclone v fpga.

[Altera_Forum]

For mixing RTL with OpenCL, check "Intel FPGA SDK for OpenCL Programming Guide, 2.1 OpenCL Library". There is no documented way of generating the OpenCL project, modifying it, and feeding it back to the compiler as you want. Doing so will very likely fail or not give the intended results. 

 Adding I/O interfaces to the project will require modifying the BSP, and generating a new one. The main document outlying this process is the same "Intel FPGA SDK for OpenCL Custom Platform Toolkit User Guide" you mentioned earlier. That involves a lot more than just modifying the board_spec.xml. You must generate all the necessary IP cores and write all the HDL code yourself to define a new I/O channel to access the specific I/O that you are trying to add, and recreate the BSP. After that you can access that I/O interface from an OpenCL kernel using the I/O channel that you defined.

[Altera_Forum]

--- Quote Start ---  For mixing RTL with OpenCL, check "Intel FPGA SDK for OpenCL Programming Guide, 2.1 OpenCL Library". There is no documented way of generating the OpenCL project, modifying it, and feeding it back to the compiler as you want. Doing so will very likely fail or not give the intended results.  Adding I/O interfaces to the project will require modifying the BSP, and generating a new one. The main document outlying this process is the same "Intel FPGA SDK for OpenCL Custom Platform Toolkit User Guide" you mentioned earlier. That involves a lot more than just modifying the board_spec.xml. You must generate all the necessary IP cores and write all the HDL code yourself to define a new I/O channel to access the specific I/O that you are trying to add, and recreate the BSP. After that you can access that I/O interface from an OpenCL kernel using the I/O channel that you defined.  --- Quote End ---    Thank you very much, that is I am finding. I will read and test the information.