OpenCL project works fine in emulation but weirdly in fpga run

[Altera_Forum]

I am currently working on an OpenCL project. The output matrix is correct on emulation, but all 0 in hardware run.  

I used channels for my kernels' communication (some of them are conditional, which mean I don't read or write to some certain channel in every loop iteration). To debug, I added printf functions and counter after my channel read/write and ran on FPGA again. The code is below (memRd kernel is a kernel I use to read data from global memory and put it in altera channel):   -------------------------------------------------------------------------------------------------------------------- __kernel __attribute__((task)) void memRd ( float *data, ......) {    ......   for (......) {    data_in = data [index];    if (......) {  write_channel_altera(data_in_ch, data_in);  printf("For the %dth write of kernel memRd, write %0.f to channe data_in_chl\n", chn_cnt, data_in);  cnh_cnt += 1;    }    }  }  ----------------------------------------------------------------------------------------------------------------------------------------- So in my FPGA run, this is what got printed out:  For the 0th write of kernel memRd, write 0 to channel data_in_ch For the 0th write of kernel memRd, write 0 to channel data_in_ch For the 0th write of kernel memRd, write 0 to channel data_in_ch For the 0th write of kernel memRd, write 0 to channel data_in_ch ...............  The entire printed text is just a replication of the 0th writing to channel operation!! I don't understand it why the same code is repeatedly executed in the same place?? ( the 1st write is supposed to appear after the 0th write)   I'll appreciate it very much if someone can give me a help!!!!