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Hi,
I have a design that works perfectly fine on aoc 16.0 (both FPGA and emulator). However, when I compile this design ( by replacing "altera" with "intel" in the opencl code) using aoc 17.1, I am giving this quartus error:
Error: kernel_system_mttkrp_2_1_16_16_II_JJ_16_2_16_16_1_8_rot_vec_channel_seq_unloader_roundrobin_c_collector_drain_reverse_seq_loader_parametrized_small_buffers_less_dsp_system: add_fileset_file: No such file /homes/nitishks/fccm-mttkrp-experiments/mttkrp-2.1.16.16-II.JJ.16.2-16.16.1.8-rot-vec-channel-seq_unloader-roundrobin_c_collector-drain_reverse_seq_loader_parametrized_small_buffers-less_dsp_8x8/build/kernel_hdl/kernel_A_feeder_channel__autorun__run_on_device_0_0_0/kernel_A_feeder_channel__autorun__run_on_device_0_0_0_function_wrapper.vhd
Error: qsys-generate failed with exit code 3: 1 Error, 0 Warnings
Info: Finished: Create block symbol file (.bsf)
Info: Starting: Create HDL design files for synthesis
Info: qsys-generate /homes/nitishks/fccm-mttkrp-experiments/mttkrp-2.1.16.16-II.JJ.16.2-16.16.1.8-rot-vec-channel-seq_unloader-roundrobin_c_collector-drain_reverse_seq_loader_parametrized_small_buffers-less_dsp_8x8/build/ip/kernel_system/kernel_system_mttkrp_2_1_16_16_II_JJ_16_2_16_16_1_8_rot_vec_channel_seq_unloader_roundrobin_c_collector_drain_reverse_seq_loader_parametrized_small_buffers_less_dsp_system.ip --synthesis=VERILOG --output-directory=/homes/nitishks/fccm-mttkrp-experiments/mttkrp-2.1.16.16-II.JJ.16.2-16.16.1.8-rot-vec-channel-seq_unloader-roundrobin_c_collector-drain_reverse_seq_loader_parametrized_small_buffers-less_dsp_8x8/build/ip/kernel_system/kernel_system_mttkrp_2_1_16_16_II_JJ_16_2_16_16_1_8_rot_vec_channel_seq_unloader_roundrobin_c_collector_drain_reverse_seq_loader_parametrized_small_buffers_less_dsp_system --family="Arria 10" --part=10AX115N2F40E2LG
Error: kernel_system_mttkrp_2_1_16_16_II_JJ_16_2_16_16_1_8_rot_vec_channel_seq_unloader_roundrobin_c_collector_drain_reverse_seq_loader_parametrized_small_buffers_less_dsp_system: add_fileset_file: No such file /homes/nitishks/fccm-mttkrp-experiments/mttkrp-2.1.16.16-II.JJ.16.2-16.16.1.8-rot-vec-channel-seq_unloader-roundrobin_c_collector-drain_reverse_seq_loader_parametrized_small_buffers-less_dsp_8x8/build/kernel_hdl/kernel_A_feeder_channel__autorun__run_on_device_0_0_0/kernel_A_feeder_channel__autorun__run_on_device_0_0_0_function_wrapper.vhd
Error: qsys-generate failed with exit code 3: 1 Error, 0 Warnings
Any suggestions what is the issue?
Thanks,
Nitish
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Could be a BSP issue or an issue specific to Quartus v17.1. What board/BSP are you using? And have you tried any other versions of Quartus? Like 17.0 or the latest 18.1 (if you have a compatible BSP)?
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It was because I was using double underscores in kernel names like "A__loader" etc. Seems like double underscores in kernel names are allowed in 16.0 but not in 17.1.
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