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Altera_Forum
Honored Contributor I
780 Views

Orthodox way for testbench in modelsim

Hi, 

 

According to Verilog spec, 

 

 

initial 

begin# 20 clk=1; 

# 40 clk=0; 

# 60 clk=1; 

# 80 clk=0; 

End 

 

 

 

 

is legal, and can be compiled under modelsim. However, if we “run 200” from restart, during execution only the first delay# 20 is hit, and the following three executions are ignored. 

Is this the excepted behavior? 

 

 

Above is actually attempt to create Verilog testbench. We read through modelsim documents, and did find useful way to create customized waveform, i.e. using value dump file, although the testbench way is not working. 

 

But no way seem to allow signal contention, or two wave definitions simultaneous to a single signal. For example, if we issue two commands: 

 

force -drive sim:/I2C_to_GPIO/clk St1 0 -cancel 2000 

force -drive sim:/I2C_to_GPIO/clk St0 0 -cancel 2000 

 

the second one overrides first, which agrees with “force” command definition in modelsim_ref. But the definition 

 

 

-drive 

(optional) attaches a driver to the object and drives the specified <value> until the object is forced again or until it is unforced with the noforce command. 

 

 

 

 

also says that drives can be attached, which I read as “allow multiple drivers”. How is this “multiple simultaneous driver” actually realized? 

 

 

 

greg
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2 Replies
Altera_Forum
Honored Contributor I
28 Views

An "orthodox" way to create a testbench is to not use force at all. Force overrides what is already on a signal, and really only meant for fault injection. 

 

As for running the testbench, the run command runs for the time specified in the command, so run 200 should run the testbench for 200 ns.# 20 delays a signal for 20*timeprecision. What have you got timeprecision set to? if it is 10 ns, then that will mean# 20 = 200 ns. 

 

Try running the simulation for longer.
Altera_Forum
Honored Contributor I
28 Views

Thanks. It was time unit problem.

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