Output Encrypted Verilog Simulation Netlist with Encrypted Sources

[DavidMapstone]

Hi,

I am trying to produce a verilog simulation netlist using quartus pro but my design contains encrypted RTL. The netlist is successfully implemented but using the quartus_eda tool, it produces an error saying: 

"Error (18580): Cannot generate netlist output files because the design includes encrypted source files"

Is there a way around this?

Many thanks,

David

[RichardTanSY_Altera]

Hi,

I hope you're doing well. May I know if the issue has been resolved, or if you still require assistance with this case?

Best regards,

Richard Tan

[RichardTanSY_Altera]

Hi,

Do you need any further assistance from my side?

Regards,

Richard Tan

[HubertG]

Hi DavidMapstone,

As we do not receive any response from you on the previous question/reply/answer that we have provided. Please login to ‘https://supporttickets.intel.com/s/?language=en_US’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.