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Altera_Forum
Honored Contributor I
820 Views

Output Timing Constraints

Hello, 

 

I'm working on a design that is ending with registers stage followed by multiplexers. I would like to know the proper way to constraint the output, i.e. the MUX timing constraint, to operate at a certain frequency (say 100 MHz). What command should I add to my SDC file? 

 

Thanks!
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10 Replies
Altera_Forum
Honored Contributor I
38 Views

Just constrain the clock to 100 MHz 

 

create_clock -period 10 -name clk100Mhz [get_ports clk] 

 

See help: http://quartushelp.altera.com/14.0/mergedprojects/tafs/tafs/tcl_pkg_sdc_ver_1.5_cmd_create_clock.htm
Altera_Forum
Honored Contributor I
38 Views

Hi Tricky, 

 

It is my understanding that defining a clock will only constrain the paths between the flip flops, so the MUX at the output will remain unconstrained. Am I wrong?
Altera_Forum
Honored Contributor I
38 Views

Are you saying that you are generating an output clock from the device? If so, you need a generated clock constraint targeted to the clock output port and a false path exception for the output clock. 

 

What is this "mux at the output" you are referring to?
Altera_Forum
Honored Contributor I
38 Views

Let me rephrase it. I have a design that has some combinational logic after registers stage and I'm asking about a way to constraint the timing of this logic cloud without adding an additional registers stage.

Altera_Forum
Honored Contributor I
38 Views

 

--- Quote Start ---  

Let me rephrase it. I have a design that has some combinational logic after registers stage and I'm asking about a way to constraint the timing of this logic cloud without adding an additional registers stage. 

--- Quote End ---  

 

 

This is confusing. Does the MUX output go to an output pin, or just another part of the design inside the FPGA?
Altera_Forum
Honored Contributor I
38 Views

It goes directly to an output pin.

Altera_Forum
Honored Contributor I
38 Views

if its going to an output pin, I highly recommend using the output regsiter. This way you can use the set_output_delay constrain to skew the clock. If it has logic before the pin, the skew will be unknown, or at least less deterministic.

Altera_Forum
Honored Contributor I
38 Views

But can't I just use the set_output_delay directly with the logic? I'm more concerned about ensuring that the combinational elements meets the required frequency of operation.

Altera_Forum
Honored Contributor I
38 Views

set_output_delay is used to describe external delay so your output can meet setup/hold timing at a destination. With logic after a register, set_output_delay doesn't include the delay through that logic. The Fitter will try to meet the external timing, but it might not be able to. This is why output registers are recommended. They give a fixed point of reference to the output pin without worrying about extra logic delays (only routing delays) to the pin. 

 

What you could do, which is messy, is use set_output_delay for the external delay and then you could use set_[max|min]_delay for the delay through the logic past the register. But adding an extra register stage is always a plus, unless you are saying that your design can't tolerate the extra cycle of latency.
Altera_Forum
Honored Contributor I
38 Views

Thanks sstrell, 

 

It's getting clearer now. I thought that set_output_delay was sufficient to constrain the logic. 

 

So now I can use the set_max_delay with a value of 10 ns from the output of the flip flop to the end of the computational logic. Will adding the set_output_delay cause any interference with the set_max_delay? Is there a rule of thumb for determining the values of input and output delay?
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