i'm trying to run a synthesis of my Design for Stratix 10 on Quartus Pro 19.4.
In my TOP ENTITY i added the PCIe HARD IP + and connected it to my entities.
I've updated the .qsf file with the pin assignments and the .ip file for the pcie. Everything seems fine to me.
I'm encountering this issue though:
Error(17670): VHDL error at PCIe_HardIP_Plus.vhd(3023): verilog module port intx_req_i does not match with type std_logic_vector of component port
Error(13657): VHDL expression error at PCIe_HardIP_Plus.vhd(3023): expression has 4 elements, but must have 9 elements
Error(16186): Can't elaborate top-level user hierarchy
I do not know what to do. The port intx_req is defined as
intx_req_i : in std_logic_vector(3 downto 0)
in the Quartus-generated .vhd file, and i'm connecting it to the same kind of signal.
It seems a problem within the generation of the IP.
What do you think?
This is an synthesis error, it is not related with the QSF assignment.
From the error message, it seem like you are not connecting the intx_req_i correctly from yuor top level. This port is a 9 bits bus but you define it as 4 bit in your top level.
I am so sorry, I just found that this is VHDL code which I am not familiar with it. Thus, I will need your design QAR file to use quartus compile and replicate the error to understand the problem.
If you can't give me the full design, then you can simplify it by remove out the other unrelated component and remain the PCIe IP that able to demonstrate the error.
Yes, maybe you can generate the IP, then set the IP top level file as the design top level, run analysis and synthesis (a&s) see if you still get the same error. If the IP not demonstrate the error, the you can generate the IP example design (ED) and perform a&s. If it pass, then you can compare it to your design top level, if the ED fail, then send the design QAR to me.
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