I just installed Quartus Prime Pro 22.2 (upgrading from 21.3) and I have run in to a strange issue with the H-tile PCIe IP core. I have the core configured for 512 bits and 16 lanes.
In 21.3, all of the clocks are listed correctly in the timing report. Under "setup summary", there are 5 clocks listed.
In 22.2, all of the PCIe clocks are missing from the timing report, with only 3 clocks listed under "setup summary". Interestingly, they are listed in the "clocks" section, but the frequency of the three HIP iopll outputs are incorrect (10/1/1 ns instead of 40/4/4 ns). Another oddity is that there are also no unconstrained paths. I tried recreating the IP core from scratch and rebuilding, but the result was the same, so this seems to be some sort of issue within Quartus itself.
I am currently downloading 21.4 and 22.1 to try to isolate what version of Quartus introduced this regression.
Clocks listed in 21.3 under "setup summary":
Clocks listed in 22.2 under "setup summary":
Has anyone else run in to this issue? Are there any known workarounds?
Edit: it appears that the 256 bit, 8 lane version is also affected, with the missing clock being pcie_hip_inst|pcie_s10_hip_ast_0|altera_pcie_s10_hip_ast_pipen1b_inst|altera_pcie_s10_hip_ast_pllnphy_inst|g_phy_g3x8.phy_g3x8|phy_g3x8|xcvr_hip_native|ch0.
Thank you for reaching out.
Just to let you know that Intel has received your support request and I am assigned to work on it.
- Can I know which user guide that you are referring on building the IP core from scratch ?
- Can I know which design example of H-tile PCie IP that you are doing ? for example AVMM, AVST or DMA ?
- Is it possible for you to share the design file here so that we can take a look on it ?
- I wasn't referencing a user guide, I just deleted the core and created a new one from the IP library, configuring the appropriate settings in the parameter editor. Originally, the core was created via TCL, which was exported from the parameter editor in a previous version of Quartus. I recreated it manually to rule out any issues in the exported TCL.
- It's the AVST core
- I suspect that the issue will appear in the AVST example design. But, I just did some quick testing, and it's also a problem on the 8 lane, 256 bit configuration of the same core, and that design is available here: https://github.com/corundum/corundum/tree/master/fpga/mqnic/S10MX_DK/fpga_10g
Edit: Actually, this design is simpler, and exhibits the same problem: https://github.com/alexforencich/verilog-pcie/tree/master/example/S10MX_DK/fpga
I am trying to reproduce the PCIe AVST example design in Quartus.
It might take sometime due to limited bandwidth that I have, get back to you soon as possible
Apologize for the inconvenience caused.
I successfully replicate your error on my side, I had escalated this to the engineering team.
I will keep this loop open, It might take some time for them to investigate the issue.
Will update here soon as possible once i get their feedback.
I had escalated to engineering, so far no feedback from them yet due to limited bandwidth.
Is there anything else I can help you at the moment?
If not I would like to have your permission to close this forum ticket.
No worries, it is just in procedure only, the forum loop is still open for comment.
Also, I will update here once I got feedback from the engineering team.
Seems to me like the ticket should remain open until the issue is resolved, no? Anyway, I suppose there is a question of the best course of action for the time being. For now, I am using 22.1. Do you know if there is a workaround for 22.2? Or is there not much that can be done until either a patch is released, or the next version of Quartus is released?
Yes you are right, by right this ticket shall remain open until the issue has been solved.
However, I had tried my best to escalate this issue on behave, there is nothing we can do at the moment until the related team find a workaround, so far i don't see any workaround at Quartus 22.2 as well.
Is there anything else that you think I can help you ? If not, can I get your permission to close this loop ?
As I will continue update this forum ASAP once I got the feedback.
Looking forward to hear back from you.
The clock will be obtainable in the new release of Quartus version 22.3.
Please try it in the newest version of the Quartus (once available).
Feel free to get back to me if it is still missing.