Hie,
Apologies for the delayed first response. The typical response time is within 24 hours, but this case was assigned to me and it was a delay from my part to provide response in time.
To answer your question, PCIe legacy interrupt is generated/initiated using message TLP (transaction layer packets) instead of a pulse or signal. The TLP of type Message Interrupt are generated internally by the PCIe hard IP of Intel FPGAs. The instructions to generate legacy TLP is available in our user guide. Refer to Pg 11-4: Chapter 11 Under Legacy Interrupts. The timing diagram describing Legacy Interrupt Assertion and De-assertion is available in Figure 11-5 and Figure 11-6.
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_c5_pcie.pdf
Please refer to the explanation from our user guide and let me know if you have further questions on generating legacy interrupt.
Regards,
Nathan
