PDN: Current Ramp Up Period setting

[Altera_Forum]

I'm trying to determine an appropriate setting for the "Current Ramp Up Period" parameter in the PDN tool for a Cyclone V device. This parameter is described as follows in the user guide: 

 some pdn tool variants allow you to add data for the core clock frequency and current ramp upperiod parameters using the pull-down menus. these values tell the tool how to calculate the currentramp up period for transient events, sometimes reducing transient current changes. the values relate tohow fast the clock for the section is running, and the length of the data pipeline. given a transient changein the input data, there are clock cycles in the pipeline for the algorithm to deliver the results. if the inputdata change activates a broad yet short pipeline, the transient is abrupt. this results in a large currentchange for the number of logic elements you are using. if the pipeline is narrow and long, the overallchange in current usage is proportionately smalleryou can set the core clock frequency parameter to a high, medium, low, or custom set of inputfrequencies. the custom option allows you to enter a specific input frequency.the current ramp up period parameter allows you to specify the number of clock cycles consumed bythe pipeline. you can select a high, medium, low, or custom setting. altera recommends using asmaller value unless you have already entered a complete design in quartus and determined the precisevalue.  So, the Current Ramp Up Period needs to be set to the longest path, from input to output, in the design? Does this still apply if the design is not a traditional datapath design but instead is more of a communications hub? In my design, the longest path is likely between Ethernet and PCIe, so I would need to figure out how many clocks it takes data to travel to/from these ports?