PLL Duty Cycle Issue

[Altera_Forum]

Hi All, 

I'm having an issue generating an output clock with any duty cycle other than 50%. The MegaWiz tool will accept the duty cycle and build the IP, but the resulting route fails during fitting with the error 'duty cycle' is set to an illegal value. The output clock I need is 600MHz and the input is 100MHz. I have a design whittled down to input clock -> PLL -> output clock. That's all I have in the design.  I understand that this is a fast clock and that the combinations of mults and divides will not be able to support every setting, but where is this documented and is this just not possible?  I'm using Quartus 17.1, And an Arria V device.  Thanks for any help here!

[Altera_Forum]

From the Arria V device handbook. You don't mention what duty cycle you're trying (or if your target device is rated to even run at 600 MHz), but maybe this will help: 

 Programmable Duty Cycle The programmable duty cycle allows PLLs to generate clock outputs with a variable duty cycle. This feature is supported on the PLL post-scale counters. The duty-cycle setting is achieved by a low and high time-count setting for the post-scale counters. To determine the duty cycle choices, the Intel Quartus Prime software uses the frequency input and the required multiply or divide rate. The post-scale counter value determines the precision of the duty cycle. The precision is defined as 50% divided by the post-scale counter value. For example, if the C0 counter is 10, steps of 5% are possible for duty-cycle choices from 5% to 90%. If the PLL is in external feedback mode, set the duty cycle for the counter driving the fbin pin to 50%. Combining the programmable duty cycle with programmable phase shift allows the generation of precise non-overlapping clocks.

[Altera_Forum]

Thanks for the reply sstrell, 

I have looked at that section of the handbook. I was expecting the megawiz tool to flag a duty cycle that would result in an error. Or give me a duty cycle as close as it can. However, the fitter fails and reports the only legal value is 50%. So should set the parameters by hand to get the desired duty cycle? There is a check box to enable setting the physical parameters thru the megawiz tool. But it wasn't clear to me how to adjust duty cycle even with that.  I think I'm ok with this clock frequency driving directly to a pin from the pll, but I have the same results with 200 MHz output clock and a %55 duty cycle. My target device is 5AGXBA1D4F27C5  Thanks