PLL Slave Ports

[Steve4]

I'm building a MAX 10 design partially using platform designer. When I try to generate the PLL, additional avalon memory mapped slave ports are included. 

This is not something that's covered in the ALT PLL user guide, additionally numerous tutorials have shown the PLL being generated with the absence of the slave ports despite the same settings.. 

Why are these ports being generated and how do I get rid of them?

[sstrell]

Can you show a screenshot of what you're seeing?

[EngWei_O_Intel · Accepted solution]

Hi Stephen Samarzia

The PLL instantiated from Platform Designer consist of a wrapper for an ALTPLL IP core and Avalon-MM slave interface. You can export this signal if you need it or leave the signal unconnected. 

Alternatively, you can instantiate the ALTPLL IP through IP Catalog. The PLL generated with this won't have this signal generated.

Thanks.

Eng Wei

[EngWei_O_Intel]

Hi Stephen Samarzia

I’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.

Eng Wei