PLL and IO Setup/Hold

[Altera_Forum]

Hi, 

 After compilation I am getting warning ID: 176441 which states: The I/O pin <name> cannot meet the timing constraints due to conflicting requirements. The I/O pin is a PLL compensated I/O, but the setup/hold requirements are in conflict with the source PLL mode(source synchronous or ZDB).  The quartus help site lists this diagnostic:   CAUSE: The specified pin is unable to meet the timing constraints because it is a PLL compensated pin and the PLL is in source synchronous mode or ZDB mode. However, it is in conflict with the setup/hold requirements on the I/O. The given I/O timing constraints will not be met.   ACTION: Check your design and make sure that your setup/hold requirements are compatible with the PLL configuration.      We suspect this warning might be the cause behind some weird intermittent problems in our system. As the warning states "the PLL is in source synchronous or ZDB mode", but our PLL is actually set up in normal mode. Regardless of what the warning says, I suppose the main problem is that the IO timing constraint does not match with the PLL setting, but where would I go to change the setup/hold requirements on the IO?  Thanks.

[Altera_Forum]

--- Quote Start ---  Hi,  After compilation I am getting warning ID: 176441 which states: The I/O pin <name> cannot meet the timing constraints due to conflicting requirements. The I/O pin is a PLL compensated I/O, but the setup/hold requirements are in conflict with the source PLL mode(source synchronous or ZDB).  The quartus help site lists this diagnostic:   CAUSE: The specified pin is unable to meet the timing constraints because it is a PLL compensated pin and the PLL is in source synchronous mode or ZDB mode. However, it is in conflict with the setup/hold requirements on the I/O. The given I/O timing constraints will not be met.   ACTION: Check your design and make sure that your setup/hold requirements are compatible with the PLL configuration.     We suspect this warning might be the cause behind some weird intermittent problems in our system. As the warning states "the PLL is in source synchronous or ZDB mode", but our PLL is actually set up in normal mode. Regardless of what the warning says, I suppose the main problem is that the IO timing constraint does not match with the PLL setting, but where would I go to change the setup/hold requirements on the IO?  Thanks.  --- Quote End ---    not sure exactly but my suspicion is that your requirement asks for clock skew while your pll mode is in normal compensating mode which deskews clock.

[Altera_Forum]

--- Quote Start ---  not sure exactly but my suspicion is that your requirement asks for clock skew while your pll mode is in normal compensating mode which deskews clock.  --- Quote End ---    That seems exactly right. Our design has an sdc file which specifies a max/min skew requirement.