PLL clocks

[ymiler]

Hi

Is there an option to generate clock by PLL like as clock gate ?

for example : 

ref clock         = 128Mhz

output clock = 120Mhz 

waveform  :

Meaning , clock 120Mhz behave like 128Mhz but without 1 clock that missing 

[AqidAyman_Intel]

Hello,

Perhaps you can refer to this design example:

https://www.intel.com/content/www/us/en/design-example/715068/intel-stratix-10-fpga-iopll-reconfiguration-clock-gating-design-example.html?wapkw=clock%20gate%20pll

Regards,

Aqid

[FvM]

Hi,
the Stratix 10 design example uses PLL-reconfiguration to switch clocks on and off. That's quite different from the intended function.
As far as I see, PLL's have no features to manipulate waveforms on a cycle-by-cycle basis. The intended waveform can be however easily obtained with regular clock gating techniques in logic cells, as suggested in Quartus handbook:

Generating gated clocks in FPGA makes only sense if you want to feed external logic. Internally gated clocks should be converted into clock enables.

[AqidAyman_Intel]

I hope the previous response was sufficient to help you proceed. As we do not receive any response from you on the previous question/reply/answer that we have provided. Please login to ‘https://supporttickets.intel.com/s/?language=en_US’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.