PLL error budget

[Altera_Forum]

I have 2 boards with 2 FPGA's (each board with its own FPGA). I'm outputting a signal out of each board which should be sync together. each board has its own local oscillator, from which each FPGA produces same frequency on each board. The should-be-sync signal is produced in this clock domain. How do I calculate the error budget between the 2 boards? 

Surely the pll has a diversion. Thx

[Altera_Forum]

If you have two boards with separate oscillators then only the clock frequencies will be approximately equal. There will be no phase/sync relationship between them. 

 If you need both boards to be 'sync together', you will need to pass the clock (or a signal derived from the clock) from one board to the other and either: use it directly; or: synchronise the logic on the second board to the signal you're sending across.  Cheers, Alex