Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)

PLL issue

Altera_Forum
Honored Contributor II
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I am using cyclone IV E PLL to generate 2.5MHZ, 10MHZ and 40MHZ. 

 

Although all output clocks are good, they are not locked between them. 

 

Is there any settings I can modify to let them locked between them. 

 

Many thanks.
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Altera_Forum
Honored Contributor II
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What exactly do you mean by "locked between them"? If they are coming from the same PLL they will be in phase, if this is what you are looking after.

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