Hello,When trying to use SystemVerilog parameter type to create a 'generic' fifo I get the following error Error (10170): Verilog HDL syntax error at generic_fifo.sv(5) near text: "type"; expecting an identifier ("type" is a reserved keyword ). Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number. Is parameter type not supported? My source code below (I double checked my files support other SV constructs), Im using quartus prime standard 17.1
module generic_fifo # ( parameter type T = logic , //It seems this is not supported parameter DEPTH = 2, parameter COUNT_SIZE = (DEPTH == 0) ? 1 : $clog2(DEPTH) ) ( input logic aclk, input logic resetn, input T data_in, input logic push, input logic pop, output logic ptr, output logic empty, output logic full, output T data_out ); T mem;Cheers, -rgarcia071
--- Quote Start --- Did you set the compiler to compile SystemVerilog or Verilog-2001 in the settings? --- Quote End --- It is set to SystemVerilog in fact I can use statements such as always_ff, and keywords like 'logic' which makes me think that parameter type T = int, and others is not supported
It is very unlikely that a type parameter would be supported. This would open it to all sorts of potential types, that you can generally work around with a LENGTH parameter. The same is true for generic types in VHDL
--- Quote Start --- It is very unlikely that a type parameter would be supported. This would open it to all sorts of potential types, that you can generally work around with a LENGTH parameter. The same is true for generic types in VHDL --- Quote End --- There is nothing un-synthesizable about a type parameter. It is just a symbolic way of representing a data type. You just need to restrict yourself to the set of synthesizable data types like you would for any variable declaration. It just a feature this tool has not gotten around to implementing it yet.
Hi,Full SystemVerilog 2009 & VHDL 2008 support is only supported by the Quartus Pro versions. All other versions may not have full language support. For more info please have a look at the following link: https://www.altera.com/products/design-software/fpga-design/quartus-prime/download.html