Path Violation in timing analyzer

[m_kumar]

Hi ,

Iam working max10 fpga , in timing analyzer i'm getting path violations can i get any help to solve this problem.

Report Timing: Found 200 setup paths (200 violated). Worst case slack is -0.575

[sstrell]

Without seeing your design and a .sdc file, there's really no way to help with this.  More details needed.

[SyafieqS]

Hi Manoj,

Maybe some information (sdc, timing report) to evaluate the issue here needed

[m_kumar]

Hi sir thanks for the reply i reached the desired timing . Problem was in my sdc file timing  values.