Path delay between two nets

[TRoa]

Hi,

I have a big Verilog based design. There is a computational block in there in the design. For example one like below:

module (aa,bb,cc,dd);

input aa ,bb, cc;

output dd;

assign dd = cc ? aa : bb;

endmodule

Now, I just want to know that what will be the path delay from aa to dd? Simple.

I am trying to use Timing Analyzer. But there are many options that I am getting confused(its my first time using this tool). I am working on Cyclone IV E device.

Can anyone give a hint how to achieve that?

[Kenny_Tan]

Timing analyzer analyse path base on register to register. What you need to do is to add aa bb cc dd as a register and write the correct constrain of it.

Since you are new to timing analysis, my suggestion is to look into the training module here

https://www.intel.com/content/www/us/en/programmable/support/training/course/odsw1115.html

Make sure you click on the follow on courses. Thanks