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Pinconfig of the FPGA to HPS. Some eroors in IOBUF

Altera_Forum
Honored Contributor II
875 Views

Hello,  

I wanted to drive the bidirectional signals from fpga to hps and hps to fpga. But I could not able to do with my code here. Please have a look my code and give me some tips.  

 

THIS CODE IS WORKING PERFECTLY, bUT IT WORKS FOR ONLY ONE DIRECTION, i WANTED TO SEE BIDIRECTIONAL RESPONCE FOR THAT I NEED TO USE IOBUF COMPONENT. I HAVE NO IDEA HOW TO IMPLEMENT THAT COMPONENT IN MY CODE. 

 

PLEASE HAVE ALOOK AND HELP ME.  

 

library IEEE; 

use IEEE.STD_LOGIC_1164.ALL; 

use ieee.std_logic_unsigned.all; 

use ieee.numeric_std.all; 

 

 

 

 

entity pinconfig is 

port( 

pins :in std_logic_vector (13 downto 0):="00000000000000"; 

signalsin :inout std_logic_vector (35 downto 0); 

signalsout :inout std_logic_vector (35 downto 0) 

 

 

); 

end pinconfig; 

 

 

architecture behav of pinconfig is 

 

 

component iobuffer 

PORT 

datain : IN STD_LOGIC_VECTOR (35 DOWNTO 0); 

oe : IN STD_LOGIC_VECTOR (35 DOWNTO 0); 

bidir : INOUT STD_LOGIC_VECTOR (35 DOWNTO 0); 

dataout : OUT STD_LOGIC_VECTOR (35 DOWNTO 0) 

 ); 

end component; 

 

 

 

 

 

 

type c is array (0 to 35, 0 to 2) of integer range 0 to 35; 

 

signal config : c := 

((0,0,0),(1,1,0),(2,2,0),(3,3,0),(4,4,3),(5,5,0),(6,6,3),(7,7,3),(8,8,3),(9,9,3),(10,10,3),(11,11,3), 

(12,12,3),(13,13,0),(14,14,3),(15,15,3),(16,16,3),(17,17,3),(18,18,1),(19,19,3),(20,20,3),(21,21,3),(22,22,3),(23,23,3), 

(24,24,3),(25,25,3),(26,26,3),(27,27,0),(28,28,3),(29,29,0),(30,30,0),(31,31,0),(32,32,0),(33,33,0),(34,34,0),(35,35,3)); 

 

--config(x,x,0) = out (fpga => gpio) 

--config(x,x,1) = in (fpga <= gpio) 

--config(x,x,2) = constant low (pin) 

--config(x,x,3) = high-Z (pin) 

signal temp: std_logic_vector (35 downto 0); 

 

begin 

 

process (pins) 

 

 

begin 

 

 

--pins(13 downto 8) = mapped to 

--pins(7 downto 2) = mapped from 

--pins(1 downto 0) = out, in or high-Z 

config(to_integer(unsigned(pins(13 downto 8))),1) <= to_integer(unsigned(pins(7 downto 2))); 

config(to_integer(unsigned(pins(13 downto 8))),2) <= to_integer(unsigned(pins(1 downto 0))); 

 

end process; 

 

 

process (signalsin, signalsout) 

begin 

 

 

case config(0,2) is 

when 0 => temp(config(0,0)) <= signalsin(config(0,1)); 

when 1 => temp(config(0,1)) <= signalsout(config(0,0)); 

when others => 

end case; 

case config(1,2) is 

when 0 => temp(config(1,0)) <= signalsin(config(1,1)); 

when 1 => temp(config(1,1)) <= signalsout(config(1,0)); 

when others => 

end case; 

case config(2,2) is 

when 0 => temp(config(2,0)) <= signalsin(config(2,1)); 

when 1 => temp(config(2,1)) <= signalsout(config(2,0)); 

when others => 

end case; 

case config(3,2) is 

when 0 => temp(config(3,0)) <= signalsin(config(3,1)); 

when 1 => temp(config(3,1)) <= signalsout(config(3,0)); 

when others => 

end case; 

case config(4,2) is 

when 0 => temp(config(4,0)) <= signalsin(config(4,1)); 

when 1 => temp(config(4,1)) <= signalsout(config(4,0)); 

when others => 

end case; 

 

** LIKE 36 PINS I WROTE CODE** 

 

 

end process; 

 

 

process (temp) 

begin 

 

 

case config(0,2) is 

when 0 => signalsout(config(0,0)) <= temp(config(0,0)); 

when 1 => signalsin(config(0,1)) <= temp(config(0,1)); 

when 2 => signalsout(config(0,0)) <= '0'; 

when others => signalsout(config(0,0)) <= 'Z'; 

end case;case config(1,2) is 

when 0 => signalsout(config(1,0)) <= temp(config(1,0)); 

when 1 => signalsin(config(1,1)) <= temp(config(1,1)); 

when 2 => signalsout(config(1,0)) <= '0'; 

when others => signalsout(config(1,0)) <= 'Z'; 

end case;case config(2,2) is 

when 0 => signalsout(config(2,0)) <= temp(config(2,0)); 

when 1 => signalsin(config(2,1)) <= temp(config(2,1)); 

when 2 => signalsout(config(2,0)) <= '0'; 

when others => signalsout(config(2,0)) <= 'Z'; 

end case;case config(3,2) is 

when 0 => signalsout(config(3,0)) <= temp(config(3,0)); 

when 1 => signalsin(config(3,1)) <= temp(config(3,1)); 

when 2 => signalsout(config(3,0)) <= '0'; 

when others => signalsout(config(3,0)) <= 'Z'; 

end case;case config(4,2) is 

when 0 => signalsout(config(4,0)) <= temp(config(4,0)); 

when 1 => signalsin(config(4,1)) <= temp(config(4,1)); 

when 2 => signalsout(config(4,0)) <= '0'; 

when others => signalsout(config(4,0)) <= 'Z'; 

 

 

** HERE ALSO SAME LIKE 36 PINS CODE** 

 

end case; 

 

 

end process; 

end behav; 

 

 

** See in attached file for normal response and input force response and output force response **
0 Kudos
1 Reply
Altera_Forum
Honored Contributor II
131 Views

Are you referring to signals inside your SoC device? You want to change the direction of both processor I/O and fabric I/O, across the internal HPS/Fabric boundary, within the device? I'm not convinced this is possible. 

 

The processor has standard interfaces for interfacing to the fabric - an AMBA AXI interface (the HPS-to-FPGA bridge). 

 

Cheers, 

Alex
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