Plan error after upgrading Quartus Pro version 20.4 to 22.4

[michib]

Hi,

I just upgrade my project for a Stratix 10 MX FPGA from 20.4 to 22.4.

With 20.4 the design run was successful but after upgrading to 22.4 I see planning errors with the same RTL / IP set:

Error(22412): The design requires at least 3 elements of type AIB_3VIO_OE but the device has only 2. 
Info(22415): AIB_3VIO_OE node(s) not associated with an IP require elements of this type: 
Info(22414): Node: AIB_3VIO_OE AIB_3VIO_CELL~u_i2c_master|u_i2c_master_top|byte_ctrl|bit_ctrl|isda_oen. 
Info(22414): Node: AIB_3VIO_OE AIB_3VIO_CELL~u_i2c_master|u_i2c_master_top|byte_ctrl|bit_ctrl|iscl_oen. 
Info(22414): Node: AIB_3VIO_OE AIB_3VIO_CELL~u_ltc2226_clk_output_gpio_top|u_ltc2226_clk_output_gpio|ltc2226_clk_output_gpio|core|i_loop[0].altera_gpio_bit_i|output_buffer.obuf~quartus_inserted_3vio_obuf_oe_wirelut. 

The GPIO for I2C master SDA/SCL is defined as bidirectional with open-drain and output enable selected:

LTC2226 clock output GPIO does is only configured for output:

The OEN path is implemented in 22.4 which was not the case with 20.4
which doesn't seem to be allowed and results in an error (all three GPIO IP files are attached).

- Could you help me to resolve that problem? 

- Do I need any additional qsf setting for this port which was not necessary in 20.4?

Best regards, 

Michael

[RichardTanSY_Intel]

Could you please share your .qar design file by archiving the project (Project > Archive Project) instead of providing three individual IP files?

This will allow me to duplicate the error in order to debug the issue effectively.

Regards,

Richard Tan

[michib]

Hi Richard, thanks for your reply. 
Sadly I cannot share the design in public.

Should I open a ticket in IPS to share the design?

Regards,

 Michael

[RichardTanSY_Intel]

Yes, you can opt to file an IPS case and share the design there. (though there is a chance a different agent may assigned to your IPS case).

Or you can share me the design files through FTP(Files Transfer Protocol), with maximum files size of 2GB. If the .qar design is more than 2GB, then we may need to use the IPS platform.

Nevertheless, I'll send you an email to facilitate the transfer of files.

Regard,

Richard Tan

[RichardTanSY_Intel]

This thread will transition to the community support.

Best Regards,

Richard Tan

[michib]

Hi Richard,

I’m very sorry for the delay. I was busy with several other tasks and had to shift the task regarding the GPIO error.

I was able to reproduce the error in a small test design.

I’d like to ask if you could have a look into the error I’m getting during plan phase and if there is a possibility to resolve it.

Short summary:

I’m trying to create 5 GPIOs in the same IO bank (3V). Two of them are used as bidirectional IO and three are output only.

Quartus is generating the ‘quartus_inserted_3vio_obuf_oe_wirelut’ which results in an error.

In Quartus 20.4 this wasn’t an issue but with 22.4 I got the AIB_3VIO_OE error.

If you need any further information do not hesitate to contact me.

Kind regards,

 Michael