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RWitt
Beginner
1,291 Views

Platform Designer - A10 PCIe SR-IOV Won't run at 8Gbps when SR-IOV is enabled.

Same core with SR-IOV disabled runs fine at the 8Gbps Gen3 speed. When SR-IOV is enabled (1 PF, no VFs, MSI-X enabled) we enumerate at 5Gbps - maximum. And the lspci-configuration-space status for Link-Status2 shows that the core did not complete the Equalization (none of the phases).

Why do we drop to 5Gbps when we enabled SR-IOV?

 

Added edit: FYI - this is a version 18.0 pcie_a10_hip core.

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5 Replies
RWitt
Beginner
29 Views

FYI - this is a version 18.0 pcie_a10_hip core.

Nathan_R_Intel
Employee
29 Views

Hie,

 

I tested using Quartus Prime Pro v18.1. If "enable SR_IOV support" is enabled, the system messages releases an error if 1 PF is selected and no VF is used.

Could you check if assigning at least 1 VF allows the link to achieve PCIe Gen3x8.

I am suspecting the equalization registers (to enabled equalization adaptation  for Gen3 Rx) require at least 1 VF for the registers to be present in the PF.

 

Regards,

Nathan

 

RWitt
Beginner
29 Views

My update 12/05/18 (pasted but edited from our other thread)

Having at least one VF when using the SR-IOV core should have nothing to do with link-speed, and I was successful building a core with 0-VFs (no error - I can't remember if it was the BARs that I needed to disable to get that error you get to go away - if I remember I'll post it).

Solution/Answer: I spent the day changing parameters and have found how to link at 8Gbps. In the "Parameters" settings tab, under the "PHY Characteristics" tab I first enabled the "Soft DFE" thinking that would help and it didn't (but I left it selected). I then checked the "Enable RX polarity inversion soft logic" box and enabled that. That was the answer, I successfully linked at 8Gbps. I then built again turning that polarity inversion off and I could only link at 5Gbps. So, there is something about the SR-IOV wrapper that makes the link bring-up different.

RWitt
Beginner
29 Views

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RWitt
Beginner
29 Views

FYI - I can't reliably get my solution to work. Seems that even with the DFE and lane reversal I still can't get to 5Gbps when we do a PCIe 'remove', FPGA-reprogram, and PCIe 'rescan' on the PCIe bus. I get 8Gbps "every" time when using the HC with just Avalon-ST selected (non-SR-IOV). Only from a system re-boot (SuperMicro) can I get 8Gbps, during the reboot the link is brought down (though no PCIe resets are generated). Seems to be an issue with resets related to PLLs loosing lock, and when I program the device the device is not running through the transceiver start-up/equalization process. Maybe there are subtle differences in the Avalon-ST and Avalon-ST SR-IOV implementations. The signal I/O is certainly different, and the way we collect configuration and status is different between the two. Maybe there is something else we are missing for generating app-reset and feedback to the HIP. Anyone else seeing these issues????