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RWitt
Beginner
871 Views

Platform Designer - A10 PCIe SR-IOV core set for (3) PFs - do the PFs have to share the 64 extended non-posted tags, or does each PF get 64 tags?

I'm trying to give each PF as many tags as possible, but are they limited to the hard-core's max support of 64 "total" (not per PF?)?

I've got a different question that asks about moving the tag support to the application layer...

 

Update: 12/04/18 - Someone pointed me to an Avalon-MM DMA document, in that document there is support for 256-tags when configured for this implementation. From the generated RTL it appears that the DMA (pseudo-application-layer logic) manages the tags and supports all 256. And in that core/configuration the user (I) can select 256-tag support. Does this mean that there is a way to tell the HIP that the application layer is managing the tags so that the HIP does not check the tag value against the value selected (since 64 is the max when Avalon-ST or Avalon-ST SR-IOV implementations are selected)?

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Nathan_R_Intel
Employee
56 Views

Hie,

 

I have answered you in the other thread, that 256-tags not supported in Arria 10 AVST. It is a document error that has been updated.

Also, Arria 10 interfaces currently does not support moving processing of tags to Application layer. 

 

Regards,

Nathan

RWitt
Beginner
56 Views

As mentioned in the other thread. 64-tags for 100Gbps designs is not acceptable. Intel needs to provide the tag support in the hard-core or allow that tag management to be done in the Application Layer. The MM-DMA core that supports 256-tags is not an option for us, and I am sure it is not for others as well.

Please escalate a request to engineering to add support for 256-tags, ASAP - for the ST core and ST-SR-IOV.

Regards,

Bob

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