Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
16606 Discussions

Platform Designer Error

Nitin1
Beginner
668 Views

I am getting this error when trying to Generate files using Quartus Standatd Edition version

 

Error: add_fileset_file: No such file C:/Users/nmistry/AppData/Local/Temp/alt8839_8898266765451528108.dir/0006_cpu_gen/simgen_tmp_0
while executing
"add_fileset_file "$file_name" OTHER PATH "$my_file""
(procedure "sub_add_generated_files" line 51)
invoked from within
"sub_add_generated_files "$NAME" "$output_directory" "$rtl_ext" "$simgen" "$plainTEXTfound""
(procedure "generate_with_plaintext" line 6)
invoked from within
"generate_with_plaintext "$NAME" "$rtl_ext" "$simgen""
(procedure "sub_sim_verilog" line 5)
invoked from within
"sub_sim_verilog niosii_system_nios2_cpu"

 

 

This error only started today and was not occuring before with this design

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4 Replies
sstrell
Honored Contributor III
655 Views

Delete the directory named after the system and try to generate again.

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Nitin1
Beginner
639 Views
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sstrell
Honored Contributor III
623 Views

Your published output directory may be corrupted.  Keep the .qsys file and all other main files in your project directory and delete the folder generated by Platform Designer that has the same name as your system.  Then try to regenerate the system.

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Nurina
Employee
610 Views

Hi,


Did the above reply solve your problem?


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