I created an AXI4 Master component in a ip-management project. I was then able to include it in platform designer, hook up the AXI master to other Avalon/AXI peripherals and generate the system. I then tried adding it to a separate project by going to File->New Component then in the pop-up GUI, I hit File->Open and point it to the _hw.tcl that was generated from and added into the original project then Finish... , "Yes, Save" in the pop up. It seems whenever I try to Generate->Generate the Testbench System... in any project I get this error: Data width must be of power of two and between 8 and 4096 and it fails to generate the RTL even though it was able to generate the RTL in the original project where I generated the template RTL for the component.
Any ideas why including it in a different project is giving me issue?
Instead of reopening the Component Editor to add your custom component to another project, either copy and paste the code and _hw.tcl file to the location of the new .qsys file or from Tools->Options add a path to point to the _hw.tcl file. I'm not sure why you're getting that particular error without seeing the system design (any errors in Messages window before trying to generate?), but there's no reason to go through Component Editor again if the component works fine in one design.
That works. Thank you. Is it common practice to have a set of directories with a _hw.tcl and associated RTL somewhere, then to point to that from Platform Designer? I know with the IP packager tool in Xilinx, this is the preferred workflow.
Another issue I am having, and I can open another thread if need be, is that it seems like when I generate t he testbench system there is a file that is supposed to wrap the RTL in the new_component.v file from the component that the top level generated platform designer RTL file is instantiating. The module name is something like <name of the platform designer>_<name of the component>. I assume inside this module, there would be an instantiation of what is in new_component.v where I wrote my RTL
# ** Error: (vsim-3033) ./../fpga_ram_sim_tb/simulation/submodules/fpga_ram_sim.v(44): Instantiation of 'fpga_ram_sim_oc_axi_lite_bfm_0' failed. The design unit was not found.
# Time: 0 ps Iteration: 0 Instance: /fpga_ram_sim_tb/fpga_ram_sim_inst File: ./../fpga_ram_sim_tb/simulation/submodules/fpga_ram_sim.v
It's up to you how you want to organize the files. You can choose to put them somewhere PD searches automatically (project directory, /ip in project directory, or Quartus installation IP directory) or add a project-specific or global path like I mentioned. Sometimes people have an IP library on a server and they point Quartus to that location.
For your second question, if you're creating a testbench system to test just this component, create a new .qsys with just your custom component in it by itself. Then when you choose to generate the testbench system, choose to add BFMs for all interfaces. That should create everything you need.
See this training for more on this:
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