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Hello Everyone,
I used Quartus 20.1 to generate the Example Design of "Arria 10 PCIe-Avalon-MM-DMA". I then used Platform Designer to add an "Avalon-MM Clock Crossing Bridge" IP core. I connected rmx_bar2 to the bridge's s0 interface and set the address range for the s0 to be 0x1_0000 - 0x1-ffff. Please see the highlighted sections in the attached diagram below.
After programming the design to the FPGA, I used the reference Linux DMA driver to explore the BARs of the PCIe FPGA device. Please see the log below.
Altera DMA 0000:d8:00.0: BAR[0] 0x39fffff08000-0x39fffff081ff flags 0x0014220c, length 512
Altera DMA 0000:d8:00.0: BAR[1] 0x00000000-0x00000000 flags 0x00000000, length 0
Altera DMA 0000:d8:00.0: BAR[2] 0x39fffff00000-0x39fffff07fff flags 0x0014220c, length 32768
Altera DMA 0000:d8:00.0: BAR[3] 0x00000000-0x00000000 flags 0x00000000, length 0
Altera DMA 0000:d8:00.0: BAR[4] 0x00000000-0x00000000 flags 0x00000000, length 0
Altera DMA 0000:d8:00.0: BAR[5] 0x00000000-0x00000000 flags 0x00000000, length 0
Altera DMA 0000:d8:00.0: BAR[0] mapped to 0x00000000edd11856, length 512
Altera DMA 0000:d8:00.0: BAR[2] mapped to 0x000000008c24ec97, length 32768
The issue here is that BAR2 only has an address range of 0x....0000 - 0x....7fff which only covers the 2 interfaces cra and MEM.s1. It does NOT cover the Bridge's s0 address range. What setting did I miss?
Thank you,
Ari
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I had to use the "Assign Base Addresses" function in Platform Designer. The address range now is as expected.
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RahulS,
I now think that the problem was actually because I did not click on "Sync System Infos" or turn on the Auto sync button.
Anyway, the Auto-assign feature should be used for all base addresses. It compacts the address space for you.
Ari
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