Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)

Platform Designer- SDRAM

TimSch
新手
2,140 檢視

Hello!

I tried the Quartus Platform Designerto create an SDRAM-Controller.
I noticed that you need to provide many information about the used chip, like timing constraints, but you don't need to provide the used clock frequency.

Does Quartus assume a certain frequency here, depending on the specified values, or does the Platform Builder recognize the clock that is attached to the generated block?

 

Thanks

Tim

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0 積分
1 解決方案
AdzimZM_Intel
員工
2,023 檢視

Hi Tim,


For the SDRAM Controller Intel FPGA IP, the controller can support standard SDRAM as described in PC100 specification by JEDEC.

Basically the spec for clock frequency in running at 100MHz.


You may visit the link below for reference of SDRAM Controller Core.

https://www.intel.com/content/www/us/en/docs/programmable/683130/23-1/core-overview-29412.html


Regards,

Adzim


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sstrell
榮譽貢獻者 III
2,119 檢視

I presume you mean Platform Designer.  And of course you have to specify clock frequency.  It's right on the General tab in the parameter editor.  Are you referring to something different?

sstrell_0-1687974997405.png

 

TimSch
新手
2,107 檢視

Thanks for your answer! It's indeed the platform designer.

I uploaded two screenshots of the tool I mean:

TimSch_0-1687991531029.png

TimSch_1-1687991546576.png

 

As you can see there is no such frequency input. Just the timings and it magically works.

 

sstrell
榮譽貢獻者 III
2,099 檢視

Oh, SDR not DDR.  I guess the parameter is not needed because as long as the design meets timing with the clock you feed the controller, it won't be an issue.  For DDR, the reference clock and the speed you plan on running the external memory are vital to the design, so they are included as parameters.

AdzimZM_Intel
員工
2,024 檢視

Hi Tim,


For the SDRAM Controller Intel FPGA IP, the controller can support standard SDRAM as described in PC100 specification by JEDEC.

Basically the spec for clock frequency in running at 100MHz.


You may visit the link below for reference of SDRAM Controller Core.

https://www.intel.com/content/www/us/en/docs/programmable/683130/23-1/core-overview-29412.html


Regards,

Adzim


AdzimZM_Intel
員工
2,001 檢視

Hi Tim,


Is there any further question in this thread?


Regards,

Adzim


AdzimZM_Intel
員工
1,967 檢視

As we do not receive any response from you on the previous reply that we have provided, I now transition this thread to community support. Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.


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