Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
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Platform Designer Tutorial Address range Error

SOkte
Novice
1,803 Views

I am following the guide AN 812: Platform Designer System Design Tutorial, I received the below error.

Error: sysA.cpu.data_master: pipeline_bridge.s0 (0x0..0xffff) is outside the master's address range (0x0..0xfff)

How to solve this structurally? (Using Platform Designer 18.1 Build 222)

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3 Replies
SOkte
Novice
1,173 Views

I have attached the address width of the CPU

In the edit assignments menu it is 17 bit wide, in the ​signals interfaces menu it is 12 bits wide

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AnandRaj_S_Intel
Employee
1,173 Views

Hi,

 

Yes,i can reproduce the error.However we can solve it

Before assign the Base address and click on lock, we have go to do system ->assign Base address.and assign the Base address and click on lock as per AN812.

AN812test.JPG

Let me know if this has helped resolve the issue you are facing or if you need any further assistance.

 

Best Regards,

Anand

SOkte1
Beginner
1,173 Views

The problem is solved.

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