Platform Designer in Quartus 18.1 Standard gives the error: Error: max10_test_ddr3.mem_if_ddr3_emif_0: 'Debugging feature set' must be set to 'No Debugging' when 'Generate SOPC Builder compatible resets' is enabled.

[AChri1]

I am trying to connect DDR3 memory with a 24bit data bus to an FPGA 10M40DAF484C7G to implement a 16bit data bus with ECC and via the FPGA connect it via a 32bit multiplexed data/address bus to an external Power PC microprocessor. I am trying to use Platform Designer in Quartus 18.1 Standard using the avalon interfaces. The FPGA will also include other circuits.

Where can the 'Debugging feature set' be set to 'No Debugging'?

Aage Christoffersen

Heinzmann Australia Pty.

[Abe]

Hi,

Can you share your design here so that we can take a look. Looks like you have to disable it in the Diagnostics tab of the EMIF controller or if you have any other diagnostic module the setting maybe in it.

[AChri1]

I have found the Feature Set and it displays No Debugging and under Included Debugging Features it states: None.

By doing things in a different order my problem is fixed.