We have a number of ModelSim PE single language (VHDL) licenses. I have quite happily used Qsys with this software for years under Quartus II 13.1 as Qsys will generate single language simulation models for the Avalon interconnect. I just started evaluating using Quartus Prime Lite 18.1 for the same purpose, but even though I select "VHDL" for the simulation or testbench model, it will always generate a Verilog file for the Avalon-MM interconnect. Even the most trivial system will generate Verilog files for the interconnect.
Is there a workaround for this to force Platform designer to generate the interconnect using just VHDL and SV like Qsys 13.1 does?
At what point did they break single language simulation of Qsys? Ideally I'd like a version of Quartus Lite/Web Edition that supports Cyclone 10 LP and Cyclone IV E but generates a purely SV and VHDL interconnect.
Refer the link below for 'Viewing the HDL Example' and 'Simulating a Qsys System'.
mixed language simulation support added in the ModelSim - Intel FPGA Edition software with Quartus 15.0.0.
please let me know if you have different concern.
The document you posted is highly misleading as the options it describes are not available in Platform Designer. Specifically the option "Allow mixed-language simulation" does not exist, so the first statement under Simulating a Qsys System "Generate the Verilog HDL, VHDL, or mixed-language simulation model for your system to use in your own simulation environment." is also incorrect because without this option it cannot generate a VHDL only simulation model, only a mixed-language simulation.
I currently have a number of ModelSim PE/VHDL licenses, these were purchased in preference to ModelSim-Altera because PE offers higher simulation speeds and is compatible with other vendor's tool chains. I do not write any Verilog code, nor do I need to maintain any, so there is no other reason for me to need Verilog support in ModelSim PE. The removal of the option to turn off "allow mixed language simulation" would force me to upgrade all of my ModelSim PE/VHDL license to ModelSim PE/Plus to maintain the same simulation performance as I currently enjoy with 13.1. I would be forced into this upgrade purely to simulate Platform Designer systems.
Can you confirm that there is no way to turn off "Allow Mixed-language Simulation" in 18.x's Platform Designer. Or has this very useful feature been removed permanently? Why does it not clearly state in the Platform Designer documentation that it is not compatible with single language HDL simulators?
Yes, document differ from reality.
I confirmed that, since the Intel Quartus v15.0 , the Modelsim-Intel FPGA edition software supports dual/mixed language simulation.
It will generate simulation model for top level module as per the specified HDL language but not the interconnect, in this case(VHDL), you may use the simulator which supports only single language.
Refer the link below for ModelSim-Intel FPGA edition software especially for 'Frequently Asked Questions',
I think you mean to say "in this case(VHDL), you may NOT use a simulator which supports only a single language." I strongly recommend that Intel add this information to their documentation as it significantly impacts a user's decision when choosing between purchasing ModelSim PE or ModelSim Intel Edition.
For our part this will significantly affect plans to migrate designs from Cyclone III to Cyclone 10, as the costs to upgrade all ModelSim PE seats and the doubling of annual maintenance have to be weighed against the very minor benefits of migrating to a device that is essentially exactly the same but with a different name written on it.