Platform designer testbench PLL component does not match entity

[gyuunyuu]

I am using Quartus 18.0 and generating ​testbench from the Platform designer (aks Qsys) system.

The Qsys system contains a PLL. When I generate testbench files, the list contains a .vho and a .vo file. One contains the PLL entity (VHDL) while the other contains the PLL module (Verilog). The input signals in both these files have no default values. Qsys usually likes to assign default values to input ports in RTL code.

The problem is that when I try to compile the simulation files, it fails. The source of the problem is how the component declaration and portmap has been done between the synthesis and simulation top level .vhd file.

The synthesis file component declaration in top level file is:

component S_PLL is port ( clk : in std_logic := 'X'; -- clk reset : in std_logic := 'X'; -- reset read : in std_logic := 'X'; -- read write : in std_logic := 'X'; -- write address : in std_logic_vector(1 downto 0) := (others => 'X'); -- address readdata : out std_logic_vector(31 downto 0); -- readdata writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata c0 : out std_logic; -- clk c2 : out std_logic; -- clk scandone : out std_logic; -- export scandataout : out std_logic; -- export c1 : out std_logic; -- clk c3 : out std_logic; -- clk c4 : out std_logic; -- clk areset : in std_logic := 'X'; -- export locked : out std_logic; -- export phasedone : out std_logic; -- export phasecounterselect : in std_logic_vector(2 downto 0) := (others => 'X'); -- export phaseupdown : in std_logic := 'X'; -- export phasestep : in std_logic := 'X'; -- export scanclk : in std_logic := 'X'; -- export scanclkena : in std_logic := 'X'; -- export scandata : in std_logic := 'X'; -- export configupdate : in std_logic := 'X' -- export ); end component S_PLL;

This changes in the simulation top level file to:

component S_PLL is port ( clk : in std_logic := 'X'; -- clk reset : in std_logic := 'X'; -- reset read : in std_logic := 'X'; -- read write : in std_logic := 'X'; -- write address : in std_logic_vector(1 downto 0) := (others => 'X'); -- address readdata : out std_logic_vector(31 downto 0); -- readdata writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata c0 : out std_logic; -- clk c2 : out std_logic -- clk ); end component S_PLL;

Why are they different? Compiling simulation files fails because the component is missing many ports.

[Vicky1]

Hi,

here we can clearly see that few ports are missing.

Could you provide your project file?(Project Menu-> Archive Project) for replication?

Thanks,

Vicky

[Vicky1]

Hi,

Could you please share the instantiation template for verilog from path as below,

Generate Menu->Instantiation template

Also check by editing those signal mention as 'export', name them & try to check testbench under *_tb directory for testbench directory.

Regards,

Vicky

[Vicky1]

Hi,

Have you resolved the issue?

Should I consider that case to be closed?

Regards,

Vicky

[gyuunyuu]

If we change the synthesis files to Verilog, the same issue is observed:

Synthesis top level:

SPRINT_OSI_S_PLL pll ( .clk (clk_33m_clk), // inclk_interface.clk .reset (rst_controller_reset_out_reset), // inclk_interface_reset.reset .read (mm_interconnect_0_pll_pll_slave_read), // pll_slave.read .write (mm_interconnect_0_pll_pll_slave_write), // .write .address (mm_interconnect_0_pll_pll_slave_address), // .address .readdata (mm_interconnect_0_pll_pll_slave_readdata), // .readdata .writedata (mm_interconnect_0_pll_pll_slave_writedata), // .writedata .c0 (pll_c0_clk), // c0.clk .c2 (pll_c2_clk), // c2.clk .scandone (), // (terminated) .scandataout (), // (terminated) .c1 (), // (terminated) .c3 (), // (terminated) .c4 (), // (terminated) .areset (1'b0), // (terminated) .locked (), // (terminated) .phasedone (), // (terminated) .phasecounterselect (3'b000), // (terminated) .phaseupdown (1'b0), // (terminated) .phasestep (1'b0), // (terminated) .scanclk (1'b0), // (terminated) .scanclkena (1'b0), // (terminated) .scandata (1'b0), // (terminated) .configupdate (1'b0) // (terminated) );

Simulation top level

SPRINT_OSI_S_PLL pll ( .clk (clk_33m_clk), // inclk_interface.clk .reset (rst_controller_reset_out_reset), // inclk_interface_reset.reset .read (mm_interconnect_0_pll_pll_slave_read), // pll_slave.read .write (mm_interconnect_0_pll_pll_slave_write), // .write .address (mm_interconnect_0_pll_pll_slave_address), // .address .readdata (mm_interconnect_0_pll_pll_slave_readdata), // .readdata .writedata (mm_interconnect_0_pll_pll_slave_writedata), // .writedata .c0 (pll_c0_clk), // c0.clk .c2 (pll_c2_clk) // c2.clk );

[gyuunyuu]

This is clearly a bug in Qsys. The only method to solve this at present would be to force the Qsys to make these ports visible.

I had a similar problem before where no VHDL files were being generated at all. I uninstalled and reinstalled Quartus and the problem went away.

If you can't see this problem on your end then this case should be closed as it is.