Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
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Platform designer very slow when opening top level system (21.1 Std)

FHint
New Contributor II
3,939 Views

Hello,

I am currently working on a FPGA project with the Quartus Prime Standard 21.1 software.
When opening the top level QSYS-file it takes forever to finally finish (multiple hours).
I have tested it with the same design on multiple machines including:

- i7 8700K with 32GB RAM and corporate Windows 10 OS

- i9 12900K with 64 GB and corporate Windows 10 OS

- i5 7500 with 8 GB RAM and standard Windows 10 OS (to make sure it wasn't the corporate Windows 10 OS)

The different hardware didn't seem to make a difference when opening the top level.

When opening a subsystem that is instantiated in the top level the Platform Designer doesn't take nearly as long. All of them open within 1 minute and one -taht includes most of the logic - takes about 20minutes to open.

When building the whole FPGA it takes 5.5h on the i7 8700K and 3h on the i9 12900K machine.
Most of the time is spent in Analysis&Synthesis: the i7 takes about 4h and the i9 2.5h here.
I assume that this is caused by the same problem that causes the top level file to be opened so slowly.

I have worked on multiple designs with this version of Quartus but have never encountered a similar issue.

The project I am currently working on consumes ~80% of the ALM and ~35% of the memory bits in the Arria 10 GX with 270kLE.

Unfortunately I cannot share the files themselves due to corporate regulations.

Are there any known issues with certain system design choices that can cause the platform designer/quartus to perform so poorly when opening or processing Analysis&Synthesis?

Best Regards,
Florian

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30 Replies
RichardTanSY_Intel
2,846 Views

It seems like you are facing performance issues with Quartus Prime Standard 21.1 when working with your FPGA project, specifically related to opening the top-level QSYS file and during the Analysis & Synthesis.

 

You may checkout this KDB to help in the PD slowness : How can I set custom value to Maximum Platform Designer memory usage field in IP Settings GUI dialog?

https://www.intel.com/content/www/us/en/support/programmable/articles/000080625.html

KDB related to PD hanging:

https://www.intel.com/content/www/us/en/support/programmable/articles/000077319.html

 

An additional workaround to improve the performance within Platform Designer is to convert instantiated IPs within the System into 'Blackbox' mode. By doing this, the IP's validation routines are disconnected from the System, reducing the computational load on the tool. When changes to an IP's parameters are needed, the mode can be switched back to 'IP' mode, allowing you to modify the parameters for a specific .ip file. To achieve this, select an instantiated IP in the System and navigate to the 'Component Instantiation' tab, then choose 'Blackbox'. This action effectively disconnects the IP from the System temporarily, alleviating the processing load. This approach can be applied to all relevant IPs, and the IP can be reintegrated into the System only when parameter changes are required.

 

Your project seems to be quite resource-intensive, consuming around 80% of the ALM and 35% of the memory bits in an Arria 10 GX device. Such high resource utilization can lead to longer analysis and synthesis times. Consider optimizing your design to reduce the resource usage, or even considering a larger FPGA if it's within the project scope.

 

Review your project settings in Quartus. Make sure that the optimization settings are appropriate for your design. Some aggressive optimization settings might lead to longer compilation times. Adjusting to other settings might help.

 

Best Regards,

Richard Tan

 

p/s: If you find any answers from the community or Intel Support to be helpful, we encourage you to mark them as the best answer or rate them 4/5 in the survey. 

 

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FHint
New Contributor II
2,828 Views

Hello Richard,

thank you for the quick and comprehensive answer!

Does the blackboxing, that you mentioned in the second paragraph, also work with the standard edition of Quartus/Platform Designer?
I can't seem to find the "Component Instantiation" tab there.

I think that my generic components could cause the issue, because I instantiate about 60 parameterized modules that I created and they even change interfaces depending on their configuration.

If blackboxing doesn't work with the standard edition I may try to create different components without any parameters to test whether they cause the problem.

Best Regards,
Florian

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sstrell
Honored Contributor III
2,815 Views

No, Component Instantiation tab is in Pro, not Standard, so that suggestion won't help you.

I have never seen it take hours to just open a .qsys file.  The compilation times you mention do not seem out of the ordinary to me for a large design, but just opening the file should at most only take a minute or two (it's basically just an XML script).  Any useful messages appear when opening the file that might shed light on what it's getting stuck on?  Are all of your files on a local drive or are you accessing any files, like IP files or custom component designs, over a network?

Any possibility of trying with a different version of Quartus?  22.1 is the latest version of Standard.

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FHint
New Contributor II
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Is the compilation time also okay when most of it is spent in A&S? The Fitter took the longest in the projects I have worked on before.

FHint_0-1693314163047.png


I worked on a project using the same FPGA (Arria 10 GX 270kLE) that consumed a higher percentage of the logic and memory and took about 1 hour to build and not nearly as long to open the top level qsys file, but I don't remeber the relation between time spent in A&S and Fitter anymore.

 

These are all the messages that appear when opening said qsys file:

FHint_1-1693314332825.png

I hope it is possible to read them. I also attached them as a file.
There doesn't seem to happen anything out of the ordinary but it took 2.5h with the i9 12900K and 64 GB RAM.

 

All of the files are on the local SSD, independent of the machines used so far.

 

I have installed and tested the Standard 22.1 edition mentioned, but it takes just as long to open the top level qsys file. I didn't build the FPGA design though because I lost hope in the solution.

 

I have also tried to "hardcode" generic components that I used to parameterize for different configurations but it doesn't seem to help. I am opening the top level file with platform designer for 1 hour now.

 

Are there any other things I can try to accelerate Platform Designer/A&S?

 

Best Regards,
Florian

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sstrell
Honored Contributor III
2,789 Views

Yes, place and route is usually much longer than synthesis, but if opening and generating the system is taking as long as you mention, that would account for the long synthesis time.  To save you time during a full compilation, you could add the system's .qip file to the project instead of its .qsys file.  That way, the compiler will use the already generated system results instead of trying to regenerate the system every time you try to recompile the project.

In the messages, do you notice where it's hanging up for long periods of time?  The messages don't show any long delays.

Since you're using Arria 10, I'd also try backing up your project and try opening this in Pro.  Arria 10 is the only family supported in both Standard and Pro.  If the project opening issue is also happening in Pro, the only other thing I can think of is that your .qsys file is corrupted somehow.

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FHint
New Contributor II
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Does adding the .qip also work for subsystems? Adding the .qip for the top level system may work, but then I'd have to open and generate the top level again in platform designer everytime something changes so I'd have to wait the 2.5h again and again.

I have seen that when generating HDL from a subsystem the .qip is created but I am not sure how to add it within Platform Designer. The only alternative I see to adding the .qsys of a subsystem is to generate the hw.tcl and add the result that ends in "export_display".

 

I checked the window multiple times while opening the top level system and it gets to the last step pretty fast. There's no line added after that and it even stays at "Done reading input file" the whole time. Then after 2.5h it suddenly finishes opening.

FHint_0-1693403079395.png

 

I had tried the Pro edition before and it opened up the top level system pretty fast, in just 1 to 2 minutes, but the Pro edition is not an option right now for this design.
Can I learn something from the difference between the Pro and Standard performance here? What does the Pro handle good that the Standard has problems with?

Is there any way I can checkt whether the top level system is corrupted or not? Does it make sense to create the top level again from scratch and add the subsystems again?

Best Regards,
Florian

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sstrell
Honored Contributor III
2,739 Views

.qip files for subsystems are generated when the top-level system is generated and should be pointed to by the top-level .qip.  You don't need to generate a subsystem separately.  Of course if you make a change to any system, then yes, you'd need to regenerate.

Why is Pro not an option?

Again, the file is probably corrupted.  Converting to Pro may be fixing the issue which is why it opens correctly in Pro.

Yes, you can try creating a new .qsys file.

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FHint
New Contributor II
2,657 Views

The Pro edition is currently not an option, because we have to reuse a large amount of older IP cores that were originally designed with the Lite and then migrated to the Standard edition. I have done a quick test and opened them with the Pro but promptly received error messages after the migration.

I have created the top level .qsys file from scratch now and it didn't seem to improve the performance but after that I generated HDL for the largest subsystem and let the platform designer create a hw.tcl for this subsystem that I then instantiated in the top level system. This seems to improve the performance, but I can not yet confirm it.

The next step will be to create this largest subsystem again from scratch to analyse whether maybe this file is corrupted.

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RichardTanSY_Intel
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Have you been able to resolve your issue based on sstrell's suggestion?

I apologize for my initial response; I didn't realize that my suggestion doesn't work for Quartus Standard.


Best Regards,

Richard Tan


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FHint
New Contributor II
2,658 Views

I have not yet been able to resolve the problem. I am currently trying to recreate existing (sub-)systems and instantiating hw.tcl of subsystems instead of .qsys to see whether this does improve performance.

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FHint
New Contributor II
2,623 Views

So far none of the (sub-)systems seems to be corrupted. When recreating the subsystems and instantiating them in the top level the platform designer starts to get really slow. So slow that for adding a single connection on top level it takes minutes if not an hour.

Can the file size per se be a problem? The top level .qsys has about 180 kB in size and the subsystems range from 10 to 90 kB. The one that has 90 kB e.g. is instantiated two times in the whole design.

Are generic components a problem? As mentioned above I instantiate the same generic component about 60 times in the whole design with different parameters. Depending on the parameters set the component chooses which FIFO to instantiate in its VHDL code (it chooses 1 of 5 FIFO). The 5 FIFO are referenced in the hw.tcl of the component and are instantiated in the VHDL code via a "if .. generate" depending on the parameter set.

Or can elaboration callback functions cause the problem? This generic component's hw.tcl also includes an elaboration callback of about 100 lines in code. Bit I had tried to "simplify" the component by splitting it up in multiple "pre defined" components with little to no parameters and lines in the callback function and the performance didn't improve.

Best Regards,
Florian

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sstrell
Honored Contributor III
2,615 Views

Are each of these 60 components completely unique?  Or are you saying that you created just one custom component and when it's instantiated, a parameter lets you select the FIFO type?  If you're having 60 completely unique components all requiring to run elaboration callbacks then that could certainly be the cause.

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FHint
New Contributor II
2,594 Views

It's one generic component with 25 parameters, but 16 of them are derived.
One of these parameters (non-derived) chooses which of the 5 FIFO is instantiated in the VHDL.
The other parameters are either used within the VHDL code, specify port widths or both.
The 16 derived parameters are set within the elaboration callback.

So yes, it's one custom component that is instantiated ~60 times with different parameters.

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FHint
New Contributor II
2,577 Views

I have now also removed the elaboration callback function from the component that is instantiated ~60 times but the performance when opening the top level system hasn't improved at all.

Is there anything else I can look into? Does the platform designer generate detailed logs when opening a file? Is it possible that the platform designer times out over and over again because it can't find certain files or tries to reach a server or anything like that?

I have observed that the platform designer uses about 1.4 GB of RAM while opening the system and has a CPU usage of about 7% for the whole period that it tries to open it. Do these values sound odd/too high?

Best Regards,
Florian

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sstrell
Honored Contributor III
2,568 Views

I'm running out of ideas.  Can you break down these components into multiple subsystems, leaving the top basically empty except for subsystem instantiations and connections?

I don't know how complex this custom component is but it is clearly the cause of the problem.  How many parameters are there?

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FHint
New Contributor II
2,543 Views

The top level system only includes subsystems and some components (e.g. PCIe HIP, some register). It instantiates one larger subsystem, that also contains some components (e.g. Avalon-MM bridge), but also 2 instances of one subsystem. These two subsystems contain the ~60 custom generic components - so ~30 for each. I tried to show the basic hierarchy in the image below:

FHint_0-1694163591670.png

The top level qsys doesn't contain anything but instantiations and connections or do I misundertsand you?

As mentioned above the custom generic component has 25 parameters but 16 of them are derived and set during the elaboration callback. Some of these parameter salso define the port widths of interfaces and one chooses the FIFO. The elaboration callback function is about 100 LoC in the hw.tcl file. The VHDL code of the custom generic component is ~700 LoC, but the VHDL shouldn't be analyzed when opening the top level qsys file anyway or is it?

Best Regards,
Florian

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sstrell
Honored Contributor III
2,525 Views

Yes, the code is analyzed when opening the system to make sure everything will work in PD.

With these details, this is a very large complicated system.  I am now not really surprised at the issue you are seeing.

Are all 60 generic components completely unique as far as parameters?  Is there no way to make any of them fixed component designs?

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FHint
New Contributor II
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There is one parameter, that chooses which FIFO is instantiated within the component. This parameter also defines most of the port's widths by setting other parameters. There are 5 different values for this parameter.

Four parameters are often shared between the instances of the custom component. These are only used in the VHDL code and do not define any port width.

Two parameters are completely unique for each instance, but are also only used in the VHDL code and do not define any interface.

One parameter is completely unique for each instance and also defines the width of a port. But the port belongs to a dummy interface that is necessary due to the problem described here: Problem with parameters when instantiating custom build component - Intel Community

 

All the other parameters are derived and depend on the first parameter mentioned (FIFO type) and are either used in the VHDL code or within the hw.tcl file to define port widths.

The only parameter that is not necessary is the last one mentioned, but without it the error described in the other thread appears.

 

I had also, as mentioned in a previous reply, tried to remove most of the parameters from the component and that didn't improve the performance.

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RichardTanSY_Intel
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Could you help to share your design .qar file (Project> Achieve Project) so we could investigate further?


Best Regards,

Richard Tan


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FHint
New Contributor II
2,252 Views

Unfortunately, as mentioned in the original post, I am not able to share the design files due to corporate regulations.

The only way would be by sharing via a secure platform, singing NDA and so on.

Best regards,
Florian

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