Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
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Platform designer very slow when opening top level system (21.1 Std)

FHint
New Contributor II
3,759 Views

Hello,

I am currently working on a FPGA project with the Quartus Prime Standard 21.1 software.
When opening the top level QSYS-file it takes forever to finally finish (multiple hours).
I have tested it with the same design on multiple machines including:

- i7 8700K with 32GB RAM and corporate Windows 10 OS

- i9 12900K with 64 GB and corporate Windows 10 OS

- i5 7500 with 8 GB RAM and standard Windows 10 OS (to make sure it wasn't the corporate Windows 10 OS)

The different hardware didn't seem to make a difference when opening the top level.

When opening a subsystem that is instantiated in the top level the Platform Designer doesn't take nearly as long. All of them open within 1 minute and one -taht includes most of the logic - takes about 20minutes to open.

When building the whole FPGA it takes 5.5h on the i7 8700K and 3h on the i9 12900K machine.
Most of the time is spent in Analysis&Synthesis: the i7 takes about 4h and the i9 2.5h here.
I assume that this is caused by the same problem that causes the top level file to be opened so slowly.

I have worked on multiple designs with this version of Quartus but have never encountered a similar issue.

The project I am currently working on consumes ~80% of the ALM and ~35% of the memory bits in the Arria 10 GX with 270kLE.

Unfortunately I cannot share the files themselves due to corporate regulations.

Are there any known issues with certain system design choices that can cause the platform designer/quartus to perform so poorly when opening or processing Analysis&Synthesis?

Best Regards,
Florian

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RichardTanSY_Intel
1,101 Views

Hi,


Do you able to share us your design?


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FHint
New Contributor II
979 Views

I have now also completely removed all of the ~60 parameterized generic custom components but the top level system still takes more than 1 hour to open. I therefore don't think that the component is causing the issue.

Is there no detailed method to log what is going on in the Platform Designer when opening a file?

Is it possible that the Platform Designer is looking for files over and over again and can't find/open them so it times out?

Is it possible that the Platform Designer is trying to reach a server that is not accessible?

What is the difference between the Pro and Standard Edition regarding Platform Designer? Maybe this way I can understand what the problem with my design is.

Best Regards,
Florian

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RichardTanSY_Intel
962 Views

You may checkout this video to learn more about the differences between Platform Designer Pro vs Standard.

https://www.youtube.com/watch?v=-okkvFUsiOc


Best Regards,

Richard Tan


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FHint
New Contributor II
945 Views

I have now found a component that enormously improves the performance when removed: the Modular Scatter-Gather DMA Intel FPGA IP.
This IP core is instantiated 8 times in the whole design and I removed all the instances.
This is the difference it makes when compiling the design:

FHint_0-1695387566243.pngFHint_1-1695387575411.png

Nothing else has been changed in the design.
Opening the top level QSYS file now only takes about 15 minutes instead of at least an hour.

All the instances of the MSGDMA share their parameters.
Is there any way to instantiate the MSGDMA without the performance impact?
Is it possible to instantiate pre-compiled code in the platform designer?

Best Regards,
Florian

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RichardTanSY_Intel
917 Views

You can checkout the guide here for ways to optimize the platform designer system.

https://www.intel.com/content/www/us/en/docs/programmable/683364/18-1/optimizing-system-performance.html


Perhaps you may try the Advanced System Design Using Platform Designer: Utilizing Hierarchy

https://www.youtube.com/watch?v=6XVS62VityA


Best Regards,

Richard Tan


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RichardTanSY_Intel
876 Views

Upon careful observation, it appears that the extended time required to open the Platform Designer is influenced by two main factors:


1) Tool Limitation: The Quartus Standard Edition tool, unfortunately, has certain limitations in comparison to the Pro Edition, leading to extended opening times.


2) Complex Qsys Design: Your design composed of numerous parameterized generic custom components, contributes to the longer duration. A notable improvement was observed (from several hours to approximately 1 hour) when removing 60 parameterized generic custom components


Given the circumstances, migrating the design to Quartus Pro is unfeasible. We will help to provide the best guidance on optimizing the Platform Designer's performance, as outlined in the user guide link I shared previously.

While the outcome may not match the efficiency of Quartus Pro, we are committed to offering the most effective suggestions.


Feel free to reach out if you have further questions or need additional assistance.


Best Regards,

Richard Tan


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FHint
New Contributor II
864 Views

Observation 2) is incorrect: as stated in my reply from September 22nd, the removal of the 60 custom generic components didn't improve the performance at all.

It was the removal of the Modular Scatter-Gather DMA Intel FPGA IP that reduced the build time and the time necessary to open the top level Qsys file.

That's why I asked whether there is any way to instantiate a pre-compiled IP core in the platform designer.

I have not yet had the time to take a look into the document and video you shared in your reply from September 25th.

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RichardTanSY_Intel
858 Views

Unfortunately, I don't think it is possible to instantiate a pre-compiled IP core in Platform Designer (Standard).


The Platform Designer (Standard) tool saves both component instantiation and system interconnects in a single .qsys file. On the other hand, Platform Designer Pro features hierarchical isolation between system interconnect and IP components. This is achieved by saving the parameters of each IP component in a .ip file, while the system interconnect is saved in a .qsys file.


Best Regards,

Richard Tan


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RichardTanSY_Intel
827 Views

Since the details of the impacted design are essential for a more in-depth analysis and resolution and without it, it will be difficult for us to further debug. With that, I will transition this thread to community support. If you have any further questions or concerns, please don't hesitate to reach out.

Thank you and have a great day!


Best Regards,

Richard Tan



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FHint
New Contributor II
785 Views

I'll try to remove everything from the design, that is not necessary to reproduce the problem and keep everything that can be shared by corporate regulations. Maybe it's enough to just keep the MSGDMA Intel IP core and basic qsys-hierarchy to cause the issue.

I can not yet say when I'll be finished with the reduced design but I'd answer this thread again when it's done - if that's ok?

Best Regards

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