Plsease urgent help in VHDL arrays

[Altera_Forum]

red <= colour_schemes[{scheme,2'd3}][3:0] 

 this is a peace of verilog code n i wanna know how to do this in vhdl ?  note:   red is std_logic_vector(3 downto 0) colour schemes is an array as follows  type colour_schemes is array(15 downto 0) of std_logic_vector(11 downto 0); signal colour_schemes_array: colour_schemes;  please need help !!!

[Altera_Forum]

assuming scheme is an integer: 

 red <= colour_schemes(scheme*4 + 3)(3 downto 0);

[Altera_Forum]

scheme is an std_logic_vector(1 downto 0); 

 I tried the way you told me.  but it gave me an error

[Altera_Forum]

I guess error is because you didnt convert scheme to an integer. Ill leave that as an exercise for you..

[Altera_Forum]

an array is accessed with (<range>) so in your case colour_schemes(scheme) where scheme is an int, an this returns a std_logic_vector, so to get the last four elements we do (3 downto 0).