Poll: Do you want the internal simulator back?

[Altera_Forum]

One of the changes in Quartus 10.0 is the missing of the internal simulator. As some people here wanted a poll: Here we go... 

 BTW: I have started a similar poll regarding the lpm-functions in the MegaWizard PlugIn-Manager at: http://www.alteraforum.com/forum/showthread.php?t=24291 (http://www.alteraforum.com/forum/showthread.php?t=24291)

[Altera_Forum]

I am a fan of the old simulator. Until Altera puts it back in Quartus II, I am using their QSIM product which works the same . (It must be run with version 11.0 of Quartus II).  

Version 11.0 is still available at the altera website under SUPPORT DOWNLOADS WEBEDITION FREE. Be sure to uninstall 11.1 and delete the subdirectory that was created for 11.1 first before installing QSIM.   FYI I have made several youtubes for Quartus at http://www.youtube.com/user/billkleitz?blend=1&ob=video-mustangbase#g/c/7bdc4877ac756557   Bill Kleitz

[Altera_Forum]

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[Altera_Forum]

--- Quote Start ---  "I think that you'll find embracing the new tools can be just as quick and efficient as using your old ones " Okay, lets give this a try. please point me to a link that will walk me trough modelsimAltera, and , give me 15 years of working knowledge in 30 min or less.. I am half way serious here, please point me to some link that will get me through chip-trip using model-sim.    --- Quote End ---    Well, this is more or less how I work. Note, I only use Verilog/VHDL. I don't use AHDL or schematics.  Quartus has a "Native Link" option to automatically call ModelSim. However, I prefer to run ModelSim manually, because it's stupid to launch ModelSim every time I make a change.  1. Create the project folder (ie, "my_project"). This is where the source code and Quartus file will reside. 2. Under "my_project", create the "simulation/modelsim". This is where ModelSim's files will reside and, more importantly, is where  3. Start ModelSim and create a new project in "my_project/simulatiion/modelsim/" called whatever.  4. Using your favourite editor, create the files - my_project/my_project.v - my_project/my_project_tb.v - my_project/simulation/modelsim/run_rtl.do - my_project/simulation/modelsim/run_gate.do  5. In ModelSim, add these files to the project 6. In ModelSim, execute the run_rtl.do file *voila*, it's simulating.  You don't need to go through this process everytime you make a change to one of the .v files. You can just recompile the file in ModelSim, restart the simulation and run it again.   When you're happy, time to move on to Quartus and gate level simulation 1. Start Quartus and create a new project in "my_project" and add the "my_project.v" file. 2. In Quartus, go to Settings -> Simulation. Make sure the EDA NetList writer is on, it's aimed at simulation/modelsim and the output is set to Verilog. 3. In Quartus, compile the project. It will dump a series of gate level Verilog models in simulation/modelsim. 4. Start ModelSim. 5. In ModelSim, execute the run_gate.do file To simulate different models, select the appropriate "my_project_xxx_vo" file.  A few important differences between run_rtl.do and run_gate.do: run_rtl.do compiles everything into a library called "work" and loads just the generic Altera Verilog libraries.  run_gate.do does not compile the original RTL code, only the gate level model generated by Quartus. It compiles everything into a library called "gate_work" and, besides Altera's libraries, loads the Cyclone IV libraries.

[Altera_Forum]

--- Quote Start ---  I do not design micky mouse systems - I design highly complex systems for aerospace applications and my company purchases large quantities of Altera parts for use in these applications.  I have always used the internal simulator - I have tried ModelSim and in comparison to the original simulator it truly sucks.  --- Quote End ---  I'm surprised that you work on complex aerospace systems without using test benches... Most of the aerospace customers I know about ask for VHDL testbenches for FPGA designs. Yes you need to learn a new tool and it can be hard at the beginning, but writing real testbenches instead of using a manual tool such as the Quartus simulator has some advantages:[list] [*]automation. After a certain level of complexity, manual verification of an IP or system can be very tedious and error prone. A testbench can do complex operations, check timing, events order, or other operations that can be difficult to do by hand just looking at waveforms [*]tracability. A test bench can write a report in a log file, and this can be useful if a history of a module needs to be recovered in the future [*]regression testing. This one is the most important in my opinion. Later in the development process, you will have some bugs and will need to do some corrections in the code. With an automatic test bench, you can very easily perform a new test after your modifications to check that you didn't change anything to the functionality. This can save a lot of debugging time.[*]code coverage. Some tools can perform automatically a code coverage report, which is also sometimes asked by some customers (although I think Modelsim Altera Edition doesn't do this)[/list]  Although I agree that the Quartus simulator is a great learning tool, it can't replace a real HDL simulator in a professional environment.

[Altera_Forum]

NativeLink only has to be re-run after a new HDL file is added to the project. if edits to the RTL are made, pushing up until you see the run command (then enter) is sufficient 

 you can also use NativeLink to create the initial .do file, edit it to taste, and configure NativeLink to run your edited .do file. you could then copy+paste vcom/vlog lines to add more source HDL

[Altera_Forum]

Altera has recently put Quartus II Version 9.1 sp2 back on their download center. (This has the internal simulator in it.) This is by far the cleanest way to create VWF files and run simulations without creating testbenches for modelsim. Version 9.1 lacks support for some of the latest high-power altera products, but for university education it is more than enough!! For a podcast on creating vwf simulation files see: http://youtu.be/7yko3pfnimq 

 Bill

[Altera_Forum]

Hiya Folks 

 I could do with still having the old Quartus simulator available.   I am updating a design packed with thousands of hours of AHDL. I am now using 11.1sp2 and need to do some simulation! What should I do please? I am happy to try and learn modelsim but how do I get round having to be in VHDL or Verilog? Thanks Dave

[Altera_Forum]

You'll have to do a gate level simulation; when you compile your design Quartus will produce a VHDL/Verilog model 

 Also, Xilinx has an app (XPort) which can convert AHDL into a VHDL netlist.

[Altera_Forum]

Check post# 28 ... (and perhaps als# 37) 

 You can simulate AHDL source with ModelSim using 'Gate Level' simulation. You have Quartus II write out a .vho netlist file in VHDL format and simulate that with ModelSim. As it is Gate Level Simulation it runs slower than RTL Simulation, but it will still be quicker than the internal Quartus II simulator. You also have to take care of proper setup and hold ties for your input signals, but if you are doing a functional test a not too fast clock will ease things. After a while you will enjoy the power of testbenches.

[Altera_Forum]

Thank you very much. I will bite the bullet 

Dave

[Altera_Forum]

Its back!! Check out Version13

[Altera_Forum]

Where do you see it in version 13?

[Altera_Forum]

I show you how to access it in my WebCast at http://www.youtube.com/watch?v=a8jakkhxlqi&list=pl7bdc4877ac756557&index=7 . Good luck, It works great! Bill

[Altera_Forum]

Thanks for that webcast. I'm glad to see the simulator really is back.

[Altera_Forum]

Actually it is not the 'old' simulator ... only the waveform editor/viewer. Underneath the simulation is executed by ModelSim. 

I did a quick test and simulated the design by Prof. Kleitz. But it looks to me that you can only enter 'top level' pins?

[Altera_Forum]

Actually it is not the 'old' simulator ... only the waveform editor/viewer. Underneath the simulation is executed by ModelSim. 

I did a quick test and simulated the design by Prof. Kleitz. But it looks to me that you can only enter 'top level' pins?

[Altera_Forum]

The default setting to use ModelSim to run the simulation didn’t work on my machine. It appears to bring up a command line window with some information, but it automatically closes before I’m able to read why it fails. To get results, I’m actually using the Quartus II Simulator. In the Simulation Waveform Editor I had to go Simulation > Options > Simulator: Quartus II Simulator.  

 I only tried top level pins, because that’s all I ever used back in day (Quartus II 9.0).   Timing simulations don’t work for me for Cyclone IV parts (only III and earlier), but that isn't too surprising.