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Port property DRIVEN_BY and dummy output ports

Altera_Forum
Honored Contributor II
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My design has a number of modules with Avalon-ST sinks and sources. None of them use packets for communication. However, it is not possible to connect sources without packet support to, for example, SGDMA sinks. Instead of adding startofpacket and endofpacket ports to the HDL of each module, I tried adding the following lines to my _hw.tcl file: 

set_port_property stream_eop DRIVEN_BY 0 set_port_property stream_sop DRIVEN_BY 0  

However, Quartus is not happy with this, and the compilation ends with errors: 

Error (12002): Port "stream_eop" does not exist in macrofunction "adc_pio_0" Error (12002): Port "stream_sop" does not exist in macrofunction "adc_pio_0"  

 

Is it really necessary to include the ports in HDL? If so, what is the use of the DRIVEN_BY port property?
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