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Valued Contributor III
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Port "out1" does not exist in primitive "AND2" of instance "STEP3"? (Code inside)

Hey guys, 

 

So I am kind of confused by this error. A quick generic google search got me on another thread in this forum where someone else was facing this problem and when he changed his entity name it was working but I tried changing AND2 to AND3 and the issue persisted. There are no other entities with the name AND2 and I am not importing any files whatsoever. Here is the full code: 

 

LIBRARY ieee;USE ieee.std_logic_1164.all; ENTITY ALU1bit IS PORT (A,B,InvertA,InvertB,CarryIn :IN STD_LOGIC; Operation :IN STD_LOGIC_VECTOR(1 DOWNTO 0); Result,CarryOut :OUT STD_LOGIC); END ALU1bit; ARCHITECTURE ARCH1 OF ALU1bit IS COMPONENT XOR2 IS PORT(in1,in2 :IN STD_LOGIC; out1 :OUT STD_LOGIC); END COMPONENT; COMPONENT AND2 IS PORT(in1,in2 :IN STD_LOGIC; out1 :OUT STD_LOGIC); END COMPONENT; COMPONENT OR2 IS PORT(in1,in2 :IN STD_LOGIC; out1 :OUT STD_LOGIC); END COMPONENT; COMPONENT FULLADDER IS PORT(in1,in2,in3 :IN STD_LOGIC; out1,out2 :OUT STD_LOGIC); END COMPONENT; COMPONENT OPERATION_EVAL IS PORT(in1,in2,in3,in4 :IN STD_LOGIC; in5 :IN STD_LOGIC_VECTOR(1 DOWNTO 0); out1 :OUT STD_LOGIC); END COMPONENT; SIGNAL AInverted, BInverted, aANDb, aORb, aXORb, Sum : STD_LOGIC; BEGIN STEP1 : XOR2 PORT MAP (A,InvertA,AInverted); STEP2 : XOR2 PORT MAP (B,InvertB,BInverted); STEP3 : AND2 PORT MAP (AInverted,BInverted,aANDb); STEP4 : OR2 PORT MAP (AInverted,BInverted,aORb); STEP5 : XOR2 PORT MAP (AInverted,BInverted,aXORb); STEP6 : FULLADDER PORT MAP (AInverted,BInverted,CarryIn,Sum,CarryOut); STEP7 : OPERATION_EVAL PORT MAP (aANDb,aORb,aXORb,Sum,Operation,Result); END ARCH1; LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY XOR2 IS PORT (in1,in2 :IN STD_LOGIC; out1 :OUT STD_LOGIC); END XOR2; ARCHITECTURE ARCH2 OF XOR2 IS BEGIN out1 <= in1 XOR in2; END ARCH2; LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY AND2 IS PORT (in1,in2 :IN STD_LOGIC; out1 :OUT STD_LOGIC); END AND2; ARCHITECTURE ARCH3 OF AND2 IS BEGIN out1 <= in1 AND in2; END ARCH3; LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY OR2 IS PORT (in1,in2 :IN STD_LOGIC; out1 :OUT STD_LOGIC); END OR2; ARCHITECTURE ARCH4 OF OR2 IS BEGIN out1 <= in1 OR in2; END ARCH4; LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY FULLADDER IS PORT (toAdd1,toAdd2,CarryIn :IN STD_LOGIC; Sum,CarryOut :OUT STD_LOGIC); END FULLADDER; ARCHITECTURE ARCH5 OF FULLADDER IS BEGIN Sum <= (toAdd1 AND (NOT toAdd2) AND (NOT CarryIn)) OR ((NOT toAdd1) AND toAdd2 AND (NOT CarryIn)) OR ((NOT toAdd1) AND (NOT toAdd2) AND CarryIn) OR (toAdd1 AND toAdd2 AND CarryIn); CarryOut <= (toAdd1 AND CarryIn) OR (toAdd2 AND CarryIn) OR (toAdd1 AND toAdd2); END ARCH5; LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY OPERATION_EVAL IS PORT (Operation1,Operation2,Operation3,Operation4 : IN STD_LOGIC; OpCode : IN STD_LOGIC_VECTOR(1 DOWNTO 0); Final : OUT STD_LOGIC); END OPERATION_EVAL; ARCHITECTURE ARCH6 OF OPERATION_EVAL IS BEGIN WITH OpCode SELECT Final <= Operation1 WHEN "00", Operation2 WHEN "01", Operation3 WHEN "10", Operation4 WHEN OTHERS; END ARCH6;
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Valued Contributor III
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Not sure why you're doing all this manual logic gate instantiation (just create a behavioral description of the adder instead of manually connecting all these logic gates), but I think there is a gate primitive named and2. The name of the output of a gate primitive would be out, not out1, so maybe that's why you're getting the error.

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