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Valued Contributor III
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Ports between blocks problem

hello every body,  

I've multi blocks of "ram_infer" and the same number of "my entire program". I want to make the output of the entire program is the input to ram_infer, but facing error problem from QII.  

 

is it correct to make on this way like below? 

putting RA0-3 as an input and output on the same time. 

 

Thanks in advance for your help. :) 

 

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wire [10:0] RA0; 

wire [10:0] RA1; 

wire [11:0] RA2; 

wire [11:0] RA3; 

 

 

generate 

genvar i; 

for (i = 0; i < IDE; i = i + 1) 

begin : IDE_block 

IDE u(global_reset_n, CLOCK_50, ram_din, di, RA0, RA1, RA2, RA3); 

end 

endgenerate 

 

 

generate  

genvar j; 

for (j=0; j < SRAM_INFERS; j = j + 1) 

begin: sram_block 

SRAM_INFERS x(CLOCK_50, write_a, sram_we,DO, RA0, RA1, RA2, RA3, ); 

end  

endgenerate 

 

 

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