Power Delivery Network (PDN) Tool

[Altera_Forum]

Hi everybody, 

 i know that PDN is just a base line guide for selecting decoupling caps. Until now i just used 100n 0402 caps on each power (VCCINT, VCCIO, VCC PLL and VCC GXB ) pin of the device (Cyclon IV GX ). That is a lot of caps :).   I decided to give it a try with PDN tool. When i enter all the relevant data i get a very small number of capacitors. Maybe 10% of what i use to do until now.  My question is ... for example when i choose Family: Cyclone IV GX, Device EP4CGX15BF14, Power Rail VCCINT the number of decoupling caps i get from PDN, is that per pin of VCCINT or all together???  thanks

[Altera_Forum]

It is the total number of capacitors. With BGA you shouldn't decouple the pins individually. Connect all VCCINT pins to the power plane through individual vias, and also connect each capacitor to the plane through individual vias. The number of BGA pins and the number of capacitors aren't necessarily related. 

Be sure that you configured the PDN with the correct current consumption on all rails. I usually use greater values that what I get from PowerPlay to have a safety margin.

[Altera_Forum]

Hi, 

 Thx for the reply.   On altera web page I read that there should be a decoupling cap on each vccint or vccio pin respectively. Do you have any thought on that? I am missing something?  Thanks

[Altera_Forum]

--- Quote Start ---   On altera web page I read that there should be a decoupling cap on each vccint or vccio pin respectively. Do you have any thought on that? I am missing something?   --- Quote End ---  Once you have decided that you need to put a decoupling capacitor across a pair of BGA vias (between VCCINT or VCCIO and a ground via), then you should have the vias tented (epoxy filled prior to the last plating step for the bottom of the PCB ). If you're tenting one power via, you may as well tent all power vias (and remove the solder mask from the bottoms of the signal vias so you can probe them with an oscilloscope).  I personally recommend tenting the vias, and placing decoupling capacitors on every single power via.  If you want to see an example design that took this approach, see the documentation on this page:  http://www.ovro.caltech.edu/~dwh/carma_board/ (http://www.ovro.caltech.edu/%7edwh/carma_board/)  The 1.2V core supply can implement a 60A load step while maintaining core regulation within the required data sheet specification.  The schematic and PCB design files are there. Feel free to download and look at them. The boards were manufactured by DDI (http://www.ddiglobal.com) and assembled by SigmaTron (http://www.sigmatronintl.com/).  Cheers, Dave

[Altera_Forum]

--- Quote Start ---  I personally recommend tenting the vias, and placing decoupling capacitors on every single power via.   --- Quote End ---     Just to follow this up, if you're using devices with 1mm BGA pitch then a footprint for 0402 caps can be created with round pads with 1mm centres.  On the back of the board these mirror the BGA pads on the top of the board and allow you to connect straight to the vias from the top layer.    This _almost_ makes the cap placement easy (though it's always a bit of a jigsaw).   My assembly guy prefers these round 0402 pads to the previous 'standard' ones I was using so they have become my default 0402 footprint.   Nial

[Altera_Forum]

Hi everybody 

 well now i am getting a little bit confused here. Should i put decoupling caps on each pin/via of FPGA's power network (VCCINT, VCCIO) or not. How do i understand the number of cap suggested by PDN tool?  Thanks in advance

[Altera_Forum]

Hi Nial 

  --- Quote Start ---  Just to follow this up, if you're using devices with 1mm BGA pitch then a footprint for 0402 caps can be created with round pads with 1mm centres.  On the back of the board these mirror the BGA pads on the top of the board and allow you to connect straight to the vias from the top layer.    --- Quote End ---  So your pads are placed in the PCB spaced between the vias, and you don't tent the vias? Did you have any issues with solder wicking into the vias?  I did try a small run of boards without tenting the vias. Inspection (flying probe and X-ray) showed there were a lot of poor contacts due to solder wicking into vias, resulting in a lot of manual rework.  The recommendation we received from SigmaTron was to tent the vias and place the 0402 caps (and any LVDS termination resistors) across the vias.  Cheers, Dave

[Altera_Forum]

--- Quote Start ---   well now i am getting a little bit confused here. Should i put decoupling caps on each pin/via of FPGA's power network (VCCINT, VCCIO) or not. How do i understand the number of cap suggested by PDN tool?   --- Quote End ---  put decoupling capacitors on every power pin.  How much money are you willing to spend, and how much risk are you willing to take if you do not put the caps on every power pin?  Talk with your PCB assembly house and PCB manufacturer and ask how they can load 0402 resistors, eg., either Nial's method where the pads are between the via holes, or the method I used, where the vias are tented.  Cheers, Dave

[Altera_Forum]

--- Quote Start ---  Hi Nial So your pads are placed in the PCB spaced between the vias, and you don't tent the vias? Did you have any issues with solder wicking into the vias?   I did try a small run of boards without tenting the vias. Inspection (flying probe and X-ray) showed there were a lot of poor contacts due to solder wicking into vias, resulting in a lot of manual rework.   The recommendation we received from SigmaTron was to tent the vias and place the 0402 caps (and any LVDS termination resistors) across the vias.   Cheers, Dave  --- Quote End ---       That was badly explained (or you're being daft!).   An 0402 footprint with 0.5mm round pads at 1mm pitch can be placed on the back of the board to mirror a pair of BGA balls on the other side.   I drop the vias centrally between the BGA pads with a short stub to the pad on the top layer. I then connect the cap straight to the via on the bottom.    You'll often get a power input and GND BGA beside each other. This allows you to have a CAP directly across their associated vias on the bottom of the board.   All my vias under the BGA are tented, it's one of the things to check on my PCB signoff checklist!   Nial

[Altera_Forum]

put decoupling capacitors on every power pin. 

 100nF caps are effectively free, and the incidental cost of placing another 20 devices per FPGA in a typical board is again almost zero.   Unless you're trying to get the costs down on a board you'll be making 10's of 1000's of you might as well follow this advice. And if you are you should have the budget to experiment.   Nial

[Altera_Forum]

--- Quote Start ---  That was badly explained (or you're being daft!).    --- Quote End ---    Both :)  I got the impression that you were putting round pads for the caps directly on the PCB bottom in the identical location to the BGA pads on the top, i.e., the round cap pads lay between the vias.    --- Quote Start ---   An 0402 footprint with 0.5mm round pads at 1mm pitch can be placed on the back of the board to mirror a pair of BGA balls on the other side.    --- Quote End ---    Its not mirroring the BGA balls, the caps go on the end of the vias.    --- Quote Start ---   I drop the vias centrally between the BGA pads with a short stub to the pad on the top layer. I then connect the cap straight to the via on the bottom.     --- Quote End ---    Now you're talking some sense :)    --- Quote Start ---   You'll often get a power input and GND BGA beside each other. This allows you to have a CAP directly across their associated vias on the bottom of the board.    --- Quote End ---    And when you don't, you steal the via from a GPIO pin, and make that GPIO pin unusable. Before I make pin assignments, I determine which power pins are missing ground pins next to them, so I can reserve appropriate GPIO pins.  The same goes for configuration signals that need pull-ups or pull-downs (if they do not route out of the BGA).    --- Quote Start ---   All my vias under the BGA are tented, it's one of the things to check on my PCB signoff checklist!    --- Quote End ---    Excellent :)  Cheers, Daft ... erm ... Dave

[Altera_Forum]

Here's a screen capture attached, looking from the bottom of a Cyclone IV board.  

Red = top layer, yellow = top silk Blue = bottom layer, sludge = bottom silk  I wasn't pin constrained but don't think I lost many user IO, I would share an odd via for decouplers or pull ups.  Nial

[Altera_Forum]

From the image, it does appear as if you have put the decoupling capacitors on round pads in a mirrored location to the BGA pads. The caps are not directly on the vias. 

 Here's a photo of the bottom of the PCB on one of the CARMA board FPGAs. Note how the decoupling caps are actually on top of the tented vias.  The square pads are slightly offset due to the fact that we initially tried not tenting the vias. However, too much solder wicked into the vias, so we had them tented (and didn't bother centering the cap pads in the vias).  Cheers, Dave

[Altera_Forum]

If I took that to my assembly guy he'd :eek: 

   --- Quote Start ---  From the image, it does appear  as if you have put the decoupling capacitors on round pads in a mirrored location to the BGA pads. The caps are not directly on the vias.  --- Quote End ---     No, that's why I kept saying they mirrored the BGA pads on the bottom of the board.   Sheesh, you academics (my dad was/is one so I know what you're like). :)     --- Quote Start ---    Here's a photo of the bottom of the PCB on one of the CARMA board FPGAs. Note how the decoupling caps are actually on top of the tented vias. The square pads are slightly offset due to the fact that we initially tried not tenting the vias. However, too much solder wicked into the vias, so we had them tented (and didn't bother centering the cap pads in the vias).   --- Quote End ---     I'm not sure if we're using 'tenting' to mean the same thing.   To me (and most on the Altium forums I think) 'tenting' means the via is covered in solder resist, but if your vias were tented you wouldn't be able to solder your caps on them.   Do you mean they've been filled (I think they use epoxy) so the solder that's down for the caps won't wick down the via?   It would be interesting to see how having the cap directly connected to the via affects it's impedance, as seen from the BGA pad, compared to having the short stub as in my example.   Is this the sort of thing you could get students to do as project work?   Another experiment would be incrementally removing decoupling caps from a working board and make noise measurements on the supplies.   Just shows there's no 'correct' way of doing things.   Nial.

[Altera_Forum]

--- Quote Start ---  If I took that to my assembly guy he'd :eek:    --- Quote End ---  I always ask the assembly company what they can handle first :)    --- Quote Start ---   No, that's why I kept saying they mirrored the BGA pads on the bottom of the board.    --- Quote End ---  Actually, you said two things; you said mirrored and you said on the ends of the vias.     --- Quote Start ---   Sheesh, you academics (my dad was/is one so I know what you're like).    --- Quote End ---  I live in the middle of nowhere, so have noone to talk to ... sniff sniff ... seriously though, I have noone to talk to about this type of PCB design, so I wanted to clearly understand what you were doing.  Just call me pedantic :)    --- Quote Start ---    I'm not sure if we're using 'tenting' to mean the same thing.   To me (and most on the Altium forums I think) 'tenting' means the via is covered in solder resist, but if your vias were tented you wouldn't be able to solder your caps on them.   Do you mean they've been filled (I think they use epoxy) so the solder that's down for the caps won't wick down the via?    --- Quote End ---  Ah, I think you are right ... sorry 'bout that.    --- Quote Start ---   It would be interesting to see how having the cap directly connected to the via affects it's impedance, as seen from the BGA pad, compared to having the short stub as in my example.    --- Quote End ---   I'm sure no stub is better :)    --- Quote Start ---   Is this the sort of thing you could get students to do as project work?    --- Quote End ---  Alas, I really am in the middle of nowhere. No students in sight ... (none that I'd give a soldering iron to anyway)  http://en.wikipedia.org/wiki/combined_array_for_research_in_millimeter-wave_astronomy    --- Quote Start ---    Another experiment would be incrementally removing decoupling caps from a working board and make noise measurements on the supplies.    --- Quote End ---  I haven't tried removing caps. I'd be afraid that I might reflow a BGA ball. The boards are 18 layers thick, with a lot of copper.     --- Quote Start ---    Just shows there's no 'correct' way of doing things.    --- Quote End ---  It is nice to discuss the possible solutions though.  Thanks for sharing your knowledge.  Cheers, Dave