I have implemented 2 Stratix V PLLs that have multiple outputs of the same frequency as shown in the below instantiation. Quartus II is optimizing the PLL such that it is combining clock outputs that have the same frequency into one output. So the below instantiation ends up only using outclk_? (0, 1, 3 and 7). Is there any way to prevent this so that the 9 different clock domains are maintained.
i_pll_360 : alt_pll_360_wrapper
PORT MAP (
refclk => iob_pll_refclk_ui, -- 100 MHz ref.
rst => '1',
locked => pll_360_locked,
outclk_0 => pll_c_gp, -- 360 MHz
outclk_1 => pll_c_cd, -- 180 MHz
outclk_2 => pll_c_d, -- 180 MHz
outclk_3 => pll_c_m, -- 90 MHz
outclk_4 => pll_c_v, -- 90 MHz
outclk_5 => pll_c_w, -- 90 MHz
outclk_6 => pll_c_c, -- 90 MHz
outclk_7 => pll_c_f0, -- 45 MHz
outclk_8 => pll_c_ch -- 45 MHz
);
