I'm having a code running on NIOS and have an external IC that make a watchdog timer. for this purpose the NIOS code make a trigger to reset the watchdog every some predefine time.
I connected a scope on the watchdog signal to see the behave.
In the NIOS I run a testing program that reset the watchdog (send signal on the WD) every 1.5 seconds.
When burning the program using the Small Boot Copier (Altera boot copier that use only one bank) the program run fine.
When I am using Advanced Boot Copier (boot loader that I wrote that uses two banks) I see that the first signal on the WD is received 4.8 seconds after watchdog boot . I added code to the Advanced Boot Copier to reset the watchdog. The Advanced Boot Copier reset the watchdog just before calling the application entry point. I see with the scope that the application starts sending reset signals to the watchdog after more than 3 seconds from the last watchdog reset (thus when the watchdog is active the nios is restarted).
When I started nios2-terminal at reset, to see when the application starts to print log massages, the delay sorted significant to be lass then 1 second and the watchdog did not reset the NIOS.
Moreover, I try to remove all the prints from the code. When there no prints there no problem, with the signal sent to the watchdog.
Do you know a way that I can use printf (using JTAG UART) that will not making such delay on startup?