Problem about SignalTab II

[Altera_Forum]

Hi, 

 Can I use the SignalTab II to check the waveform of some output ports or registers when I debug my codes in Nios II IDE 5.1?   Thanks.

[Altera_Forum]

When you enable signalTap II, quartus ii just adds some hardware to your design in order to enable the signals acquisition.  

 I guess there is not problem with this.

[Altera_Forum]

Yes, just check that you have left enough space in your FPGA to let Quartus II use the logic cells and the RAM needed by the SignalTap operation.

[Altera_Forum]

The NIOS IDE and SignalTapII can use the JTAG at the same time (I know this works on bitblaster, but can't confirm other JTAG hardware.) 

 *EDIT: I have only verified this for v7.1 and 8.0.  You just need to make sure the processor is stopped in the NIOS IDE before you reprogram the FPGA, or else the programmer complains about JTAG being in use.

[Altera_Forum]

What is important is this: Though SignalTap And NIOS Debug both require JTAG and their operations must be mutually exclusive, they check for different things when they communicate over JTAG. SignalTap checks for the correct hardware image before acquiring the data. IDE checks for sysid (if you included it in SOPC system) and for the h/w image. So, The caveats in this experiment are following: 

1. You cannot have continuous run of Signal Tap (i.e. Auto mode) when you are in Debug mode of NIOS. 2. Running the NIOS in debug mode will stop the processor momentarily. If you have a NIOS signal as trigger in SignalTap, this can cause a problem. 3. Program the FPGA through SignalTap and NOT through the Programmer.